AT89C2051-12SC Atmel, AT89C2051-12SC Datasheet - Page 6

• Manufacturer Part Number: AT89C2051-12SC
• Manufacturer: Atmel

Specifications of AT89C2051-12SC

• Cpu Family: 89C
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 12MHz
• Interface Type: UART
• Program Memory Type: Flash
• Program Memory Size: 2KB
• Total Internal Ram Size: 128Byte
• # I/os (max): 15
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 6V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: SOIC
• Lead Free Status / Rohs Status: Not Compliant

7. Restrictions on Certain Instructions
7.1
7.2
8. Program Memory Lock Bits
6
Branching Instructions
MOVX-related Instructions, Data Memory
AT89C2051
The AT89C2051 and is an economical and cost-effective member of Atmel’s growing family of
microcontrollers. It contains 2K bytes of Flash program memory. It is fully compatible with the
MCS-51 architecture, and can be programmed using the MCS-51 instruction set. However,
there are a few considerations one must keep in mind when utilizing certain instructions to pro-
gram this device.
All the instructions related to jumping or branching should be restricted such that the destination
address falls within the physical program memory space of the device, which is 2K for the
AT89C2051. This should be the responsibility of the software programmer. For example, LJMP
7E0H would be a valid instruction for the AT89C2051 (with 2K of memory), whereas LJMP 900H
would not.
LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR – These unconditional branching
instructions will execute correctly as long as the programmer keeps in mind that the destination
branching address must fall within the physical boundaries of the program memory size (loca-
tions 00H to 7FFH for the 89C2051). Violating the physical space limits may cause unknown
program behavior.
CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ – With these conditional branching
instructions the same rule above applies. Again, violating the memory boundaries may cause
erratic execution.
For applications involving interrupts the normal interrupt service routine address locations of the
80C51 family architecture have been preserved.
The AT89C2051 contains 128 bytes of internal data memory. Thus, in the AT89C2051 the stack
depth is limited to 128 bytes, the amount of available RAM. External DATA memory access is
not supported in this device, nor is external PROGRAM memory execution. Therefore, no MOVX
[...] instructions should be included in the program.
A typical 80C51 assembler will still assemble instructions, even if they are written in violation of
the restrictions mentioned above. It is the responsibility of the controller user to know the physi-
cal features and limitations of the device being used and adjust the instructions used
correspondingly.
On the chip are two lock bits which can be left unprogrammed (U) or can be programmed (P) to
obtain the additional features listed in the
Table 8-1.
Note:
1
2
3
1. The Lock Bits can only be erased with the Chip Erase operation.
Program Lock Bits
Lock Bit Protection Modes
LB1
U
P
P
LB2
U
U
P
Protection Type
No program lock features
Further programming of the Flash is disabled
Same as mode 2, also verify is disabled
(1)
Table
8-1.
0368H–MICRO–6/08