A42MX24-PQ208 MICROSEMI, A42MX24-PQ208 Datasheet - Page 73

• Manufacturer Part Number: A42MX24-PQ208
• Manufacturer: MICROSEMI

Specifications of A42MX24-PQ208

• Family Name: 42MX
• Number Of Usable Gates: 36000
• Number Of Logic Blocks/elements: 912
• # Registers: 1410
• # I/os (max): 176
• Process Technology: 0.45um (CMOS)
• Operating Supply Voltage (typ): 3.3/5V
• Logic Cells: 912
• Device System Gates: 36000
• Propagation Delay Time: 2.5/1.8ns
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Table 37 •
Parameter Description
Input Module Predicted Routing Delays
t
t
t
t
t
Global Clock Network
t
t
t
t
t
t
TTL Output Module Timing
t
t
t
t
t
t
t
t
t
Notes:
1. For dual-module macros, use t
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
5. Delays based on 35 pF loading.
IRD1
IRD2
IRD3
IRD4
IRD8
CKH
CKL
PWH
PWL
CKSW
SUEXT
DLH
DHL
ENZH
ENZL
ENHZ
ENLZ
GLH
GHL
LSU
device performance. Post-route timing analysis or simulation is required to determine actual performance.
obtained from the Timer utility.
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, V
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Input LOW to HIGH
Input HIGH to LOW
Minimum Pulse
Width HIGH
Minimum Pulse
Width LOW
Maximum Skew
Input Latch External
Set-Up
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
G-to-Pad LOW
I/O Latch Output Set-Up
5
PD1
FO=32
FO=486
FO=32
FO=486
FO=32
FO=486
FO=32
FO=486
FO=32
FO=486
FO=32
FO=486
+ t
RD1
+ t
2
PDn
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
‘–3’ Speed
3.0
3.3
3.0
3.3
0.0
0.0
0.7
, t
CO
CCA
+ t
2.6
2.9
3.2
3.5
4.8
4.4
4.8
5.1
6.0
0.8
0.8
3.4
4.0
3.6
3.9
7.2
6.7
4.8
4.8
RD1
= 3.0V, T
+ t
v6.1
‘–2’Speed
PDn
3.3
3.7
3.4
3.7
0.0
0.0
0.7
, or t
J
= 70°C)
4.4
8.0
7.5
PD1
2.9
3.2
3.6
3.9
5.3
4.8
5.3
5.7
6.6
0.8
0.8
3.8
4.4
4.0
5.3
5.3
+ t
RD1
‘–1’ Speed
3.8
4.2
3.8
4.2
0.0
0.0
0.8
+ t
SUD
3.2
3.6
4.0
4.4
6.1
5.5
6.0
6.4
7.5
1.0
1.0
4.3
5.0
4.5
5.0
9.1
8.5
6.0
6.0
, whichever is appropriate.
‘Std’ Speed
4.5
4.9
4.5
4.9
0.0
0.0
1.0
40MX and 42MX FPGA Families
10.7
3.8
4.3
4.8
5.2
7.1
6.5
7.1
7.6
8.8
1.1
1.1
5.0
5.9
5.3
5.8
9.9
7.2
7.2
‘–F’ Speed
6.3
6.9
6.3
6.9
0.0
0.0
1.4
10.0
10.0
10.6
12.4
14.9
13.9
10.0
10.0
5.3
6.0
6.6
7.3
9.1
1.6
1.6
7.1
8.3
7.4
8.2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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