ELANSC400-66AC AMD (ADVANCED MICRO DEVICES), ELANSC400-66AC Datasheet - Page 94

• Manufacturer Part Number: ELANSC400-66AC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ELANSC400-66AC

• Cpu Family: Elan
• Device Core Size: 16/32Bit
• Frequency (max): 66MHz
• Interface Type: ISA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 292
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

Notes:
1. The ROMCSx address decode is programmable for an early decode (via bit 5 in CSC index 23h, 25h, and 27h). The early
2. When a x32 DRAM or VL bus is enabled, additional delay must be added to accommodate for the delay through the external
3. There are two types of programmable wait states. The first programmable wait state is always used in the first access for
4. If wait states are added via the deassertion of IOCHRDY, the data setup time to IOCHRDY assertion is 0 ns (minimum).
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address-decode is available to provide the ROMCSx by qualifying the address signals only; it is not qualified with the com-
mands (ROMRD, ROMWR). The timing parameter t2a pertains to the early address-decode feature being enabled (ROMCSx
is address-decode only). Parameters t2b and t2c are observed when the early address-decode feature is disabled (ROMCSx
is address-decode qualified with command). The early decode can be enabled for both Fast-mode and Normal-mode ROM
accesses.
data buffers required for the SD bus in this mode.
either burst or non-burst supported device. It starts at the assertion of the chip select or at the transition of SA3–SA0, whic h-
ever occurs later. The second programmable wait state is used only for any subsequent burst read accesses to a burst mode
ROM device. It starts at the transition of SA3–SA0. The burst address valid duration depends on which wait state is used. If
the wait state is set to zero, then the minimum address duration is 30 ns (one bus clock cycle).
SD15–SD0
SA25–SA4
(x32 ROM)
DBUFRDH
DBUFRDL
R32BFOE
SA3–SA0
ROMCSx
DBUFOE
ROMWR
ROMRD
D15–D0
Figure 25. Fast Mode 8-/16-/32-Bit ROM/Flash Memory Read Cycle
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
t1
t2b
t27
t8
t7 t7
t9
t9
t4
t1
t6
t6
t25
t28