TP3403V National Semiconductor, TP3403V Datasheet - Page 2

• Manufacturer Part Number: TP3403V
• Manufacturer: National Semiconductor

Specifications of TP3403V

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / Rohs Status: Not Compliant

Connection Diagrams
Pin Descriptions
GND
V
MCLK
(TP3401 only) requires a CMOS logic level clock input from
MCLK XTAL This pin is the 2 048 MHz Master Clock in-
(TP3402 3403 put which requires either a crystal to be con-
only)
XTAL2
(TP3402 and amplifier
TP3403 only)
MBS FS
(TP3401 and Sync input which may be clocked at 4 kHz
TP3403 only) to synchronize Transmit bursts from a num-
BCLK
FS
CC
a
See NS Package Number J20A
Name
Order Number TP3401J
C
TP3401 DASL
Negative power supply pin normally 0V All
analog and digital signals are referred to this
pin
Positive power supply input which must be
The 2 048 MHz Master Clock input which
a stable source Must be synchronous with
BCLK
nected between this pin and XTAL2 or a
CMOS logic level clock from a stable source
which must be synchronous with BCLK
This pin is the output side of the oscillator
In Master Mode this pin is the Master Burst
ber of devices at the Master end only The 4
kHz should be nominally a square wave sig-
nal If not used leave this pin open In Slave
mode this pin is a short Frame Sync output
suitable for driving another DASL in Master
Mode to provide a regenerator (i e range-ex-
tender) capability
Bit Clock logic signal which determines the
data shift rate for B channel data on the digi-
tal interface side of the device In Master
mode this pin is an input which may be any
multiple of 8 kHz from 256 kHz to
2 048 MHz but must be synchronous with
MCLK In Slave mode this pin is an output at
2 048 MHz
In Master mode only this pin is the Transmit
Frame Sync pulse input requiring a positive
edge to indicate the start of the active chan-
nel time for transmit B channel data into B
FS
MCLK In Slave mode only this pin is a digi-
a
5V
a
must be synchronous with BCLK and
g
5%
TL H 9264– 2
Description
See NS Package Number J20A
Order Number TP3402J
TP3402 DASL
x
2
FS
B
B
TS
D
D
DCLK DEN
Crystal specifications 2 048 MHz parallel resonant R
20 pF load Crystal tolerance should be
ture
x
r
x
r
b
r
TL H 9264 – 15
Name
LSD
tal output pulse which indicates the 8-bit pe-
riods of the B1 channel data transfer at both
B
In Master mode only this pin is the Receive
Frame Sync pulse input requiring a positive
edge to indicate the start of the active chan-
nel time of the device for receive B channel
data out from B
with BCLK and MCLK In Slave mode only
this pin is a digital output pulse which indi-
cates the 8-bit periods of the B2 channel
data transfer at both B
Digital input for B1 and B2 channel data to
be transmitted to the line must be synchro-
nous with BCLK
Digital output for B1 and B2 channel data
received from the line
In Master mode only this pin is an open-
drain output which is normally high imped-
ance but pulls low during both B channel ac-
tive receive time slots In Slave mode only
this pin is an output which is normally high
impedance and pulls low when a valid line
signal is received
Digital input for D channel data to be trans-
mitted to the line must be synchronous with
DCLK
Digital output for D channel data received
from the line
In Master mode this pin is an input for the
16 kHz serial shift clock for D channel data
on D
with BCLK It may also be re-configured via
the Control Register to act as an enable in-
put for clocking the D channel interface syn-
chronized to BCLK In Slave mode this is a
16 kHz clock output for D channel data
x
and B
x
and D
See NS Package Number V28A
r
TP3403 Package Information
Order Number TP3403V
r
which should be synchronous
Description
r
FS
g
75 ppm for aging and tempera-
b
must be synchronous
x
and B
S s
r
TL H 9264 – 16
100
with a