MC68HC711KS2CFN3 Freescale Semiconductor, MC68HC711KS2CFN3 Datasheet - Page 73

• Manufacturer Part Number: MC68HC711KS2CFN3
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC711KS2CFN3

• Cpu Family: HC11
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI/SPI
• Program Memory Type: ROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

M68HC11K Family
MOTOROLA
$006A
$006B
$0062
$0063
$0064
$0065
$0066
$0067
$0068
$0069
Addr.
Timer Period 1 Register
Timer Period 2 Register
Timer Period 3 Register
Timer Period 4 Register
Pulse Width Modulation
Pulse Width Modulation
Pulse Width Modulation
Pulse Width Modulation
Pulse Width Modulation
Pulse Width Modulation
Pulse Width Modulation
Pulse Width Modulation
Pulse Width Modulation
Pulse Width Modulation
Timer Enable Register
Register (PWSCAL)
Register (PWCNT1)
Register (PWCNT2)
Register (PWCNT3)
Register (PWCNT4)
Timer Counter 1
Timer Counter 2
Timer Counter 3
Timer Counter 4
Register Name
Timer Prescaler
See page 215.
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Figure 4-1. Register and Control Bit Assignments (Sheet 9 of 11)
(PWPER1)
(PWPER2)
(PWPER3)
(PWPER4)
(PWEN)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
TPWSL
Operating Modes and On-Chip Memory
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
0
0
0
0
0
0
0
0
0
0
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= Unimplemented
DISCP
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
6
0
0
0
0
0
0
0
0
0
0
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
5
0
0
0
0
0
0
0
0
0
0
0
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
4
0
0
0
0
0
0
0
0
0
0
0
R
Operating Modes and On-Chip Memory
= Reserved
PWEN4
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
3
0
0
0
0
0
0
0
0
0
0
PWEN3
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
2
0
0
0
0
0
0
0
0
0
0
U = Undefined
PWEN2
Control Registers
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
1
0
0
0
0
0
0
0
0
0
0
Technical Data
PWEN1
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
0
0
0
0
0
0
0
0
0
0
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