21554AA Intel, 21554AA Datasheet - Page 7

• Manufacturer Part Number: 21554AA
• Manufacturer: Intel

Specifications of 21554AA

• Lead Free Status / Rohs Status: Supplier Unconfirmed

1.3.2
1.3.3
1.3.4
1.3.5
21554 PCI-to-PCI Non-Transparent Bridge Evaluation Board User’s Guide
Test Point Pods
The DE1B55401’s 64 test points are presented in 16-pin pods, which are header type connectors.
Each pod contains eight (8) individual test point pairs. There are 15 pods on the board. The pods
are arranged on the board in three groups:
Jumpers
Switch Packs
J19, J20, and J21 control the options at power up, the direction of the REQ# and GNT# lines, and
the on-board parallel ROM functions. See
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The J4, J5, J6, J7, and J8 pods are the PCI 64-bit extension signals.
The J9, J10, J11, J12, J13, J14, J17, and J18 pods are the control, address and data, and clock
signals for the secondary PCI bus.
The J15 and J16 pods are the parallel ROM data and address lines.
J22, J23, J24, and J25 can have mechanical jumpers installed. They control ROM and socket
enabling. See
Zero-ohm resistors must me soldered on or off the board to configure the clock and clamping
options. See
E1 is a voltage regulator which generates 3.3V s_vio. See
E2 is the 21554 PCI-to-PCI Bridge IC.
E3 is a clock buffer IC.
E4 is the serial ROM.
E5 is the parallel ROM and E7, E8, and E9 are address latches for the parallel ROM.
E6 is an empty external ROM socket that is mounted the reverse side of the board behind the
address latches. This socket can be used to attach a ROM emulator.
Y1 is a 33.333 MHz crystal oscillator that can be used for an independent local clock signal.
L1 is a LED indicator that shows the LOO bit (LED On or Off bit) which is switched through
software. This LED can light if jumper J22 is installed.
Section 1.6
Section
1.5.
and
Section
1.7.
Section
1.4,
Chapter
Section
2, and
Chapter
1.7.
3.
Introduction
1-7