MT49H8M32FM-33 Micron Technology Inc, MT49H8M32FM-33 Datasheet
MT49H8M32FM-33
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MT49H8M32FM-33 Summary of contents
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... DD DD ® ) 144-Ball µBGA Valid Part Numbers Part Number Description MT49H8M32FM-xx MT49H16M16FM-xx 16 Meg x 16 ® 256Mb reduced latency DRAM ® ) contains 8 banks x32Mb of memory Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. ...
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... Overview .30 EXTEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 SAMPLE/PRELOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 BYPASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Reserved for Future Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Recommended DC Operation Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 pdf: 09005aef81121545/source: 09005aef810c0ffc 256M_16_32_RLDRAM1TOC.fm - Rev F 8/05 EN 256Mb: x16, x32 2.5V V EXT Micron Technology, Inc., reserves the right to change products or specifications without notice 1. 1. RLDRAM DD DD Table of Contents © ...
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... TAP Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Figure 29: TAP Timing .31 Figure 30: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Figure 31: Output Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Figure 32: 144-Ball µBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 pdf: 09005aef81121545/source: 09005aef810c0ffc 256M_16_32_RLDRAM1LOF.fm - Rev F 8/05 EN 256Mb: x16, x32 2.5V V EXT Micron Technology, Inc., reserves the right to change products or specifications without notice 1. 1. RLDRAM DD DD List of Figures © ...
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... Address Widths at Different Burst Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Table 6: Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Table 7: Description of Commands .10 Table 8: AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Table 9: Clock Input Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 10: RLDRAM Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 12: Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Table 14: TAP DC Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Table 15: Identification Register Definitions .33 Table 16: Scan Register Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Table 17: Instruction Codes ...
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... Bank 4 Data Valid Data Read Strobe DVLD DQS[3:0], DQS#[3:0] Note: When the setting is used, A18 is a “Don’t Care.“ pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN 256Mb: x16, x32 2.5V V EXT A0–A18, B0, B1, B2 Column Address Row Address Buffer Buffer Row Decoder ...
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... DVLD DQS[1:0], DQS#[1:0] Notes: 1. When the setting is used, A19 is a “Don’t Care.” the 16 Meg x 16 configuration, only DQS[1:0] and DQS#[1:0] are used. pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN 256Mb: x16, x32 2.5V V EXT A0–A19, B0, B1, B2 Column Address ...
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... Notes Function. This signal is internally connected and has parasitic characteristics of an I/O signal. This may optionally be connected to GND Function. This signal is internally connected and has parasitic characteristics of an DQS signal. This may optionally be connected to GND. pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN 256Mb: x16, x32 2. ...
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... Data read strobes: DQSx and DQSx# are the differential data read strobes. During READs, they are transmitted by the RLDRAM and edge-aligned with data. DQSx# is ideally 180 degrees out of phase with DQSx. DQS0 and DQS0# are aligned with DQ0–DQ7. DQS1 and DQS1# are aligned with DQ8– ...
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... A represents a valid address BA represents a valid bank address the x32 configuration A19 is not used. 3. See above table; address widths at different burst lengths. 4. Only A(17:0) are used for the MRS command. pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN 256Mb: x16, x32 2.5V V x32 18:0 17:0 CS# ...
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... AREF The AREF is used during normal operation of the RLDRAM to refresh the memory content of a bank. The command is nonpersistent must be issued each time a refresh is required. The value on the BA(2:0) inputs selects the bank. The refresh address is generated by an internal refresh controller, effectively making each address bit a “ ...
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... Parameter only valid within one DQS/DQ group, e.g., DQS0, DQS0#, and DQ0–DQ7; DQS1, DQS1#, and DQ8–DQ15. 5. The rising and falling edges of DVLD are referenced to falling edges of DQS. Figure 4: Clock Command/Address Timings CK# CK CMD, ADDR pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN 256Mb: x16, x32 2.5V V -33 Symbol Min Max Min t CK 3.3 4 ...
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... Notes: 1. MRS: MRS command RFx: REFRESH Bank x AC: any command. 2. During 3. When the RLDRAM is powered up with the matched impedance mode inactive, the 2,048 cycles between the eight REFRESH commands are not required. These cycles are necessary in order to calibrate the output drivers. pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2 ...
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... CK and CK# input slew rate must be ≥1V/ns (≥2V/ns if measured differentially CK#. 10. The value of V variations in the DC level of the same. 11. CK and CK# must cross within this region. 12. CK and CK# must meet at least V 13. Minimum peak-to-peak swing. pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN 256Mb: x16, x32 2.5V V Symbol Min -0 ...
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... CMD Note: MRS: MRS command AC: any command. pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN 256Mb: x16, x32 2. MRSC must be met before any command can be issued to the RLDRAM. COD DON’T CARE MRS NOP NOP t MRSC Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Figure 9: Mode Register Bit Map A(17:6) Reserved Notes: 1. Bits A(17:6) must be set to zero. 2. HSTL-compliant current specification. 3. Automatic I/O impedance calibration is activated in matched mode. pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN 256Mb: x16, x32 2. Driver Matched Burst 1 Strength Mode Length 2 A3 Burst Length ...
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... Configuration Table The table below shows the different RLDRAM configurations that can be programmed into the mode register for different operating frequencies. The READ and WRITE latency and well as in nanoseconds. The shaded areas correspond to configurations that are not allowed. Table 10: ...
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... WRITE Command CS# AS# WE# REF# DM(1:0) A(20:0) BA(2:0) Note: A: address BA: bank address DM: data mask. Figure 11: Basic WRITE Burst Timing CK pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN 256Mb: x16, x32 2. DON’T CARE Write Latency Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Notes: 1. A/BAx: address A of bank x WR: WRITE Dxy: data y to bank x WL: WRITE latency. 2. Any free bank may be used in any given CMD. The sequence shown is only one example of a bank sequence. pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN 256Mb: x16, x32 2.5V V -33 Min/Max t 0.5 DS ...
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... Notes: 1. A/BAx: address A of bank x WR: WRITE Dxy: data y to bank x WL: WRITE latency. 2. Any free bank may be used in any given CMD. The sequence shown is only one example of a bank sequence. pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN 256Mb: x16, x32 2.5V V EXT ...
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... DQ D0a D0b D0c DQSx DQSx# Note: A/BAx: address A of bank x WR: WRITE Dxy: data y to bank x WL: WRITE latency RD: READ Qxy: data y from bank x RL: READ latency. pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN 256Mb: x16, x32 2. NOP WR NOP A A BA2 BA4 ...
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... Figure 17: READ Command CK# CK CS# AS# WE# REF# A(20:0) BA(2:0) Note: A: address BA: bank address. pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN 256Mb: x16, x32 2. DQSQ is derived at each DQS clock edge and is not cumulative CKH, CKL DQSQ(MAX DON’T CARE ...
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... Timing Parameters Symbol CKH t CKL t CKDQS t DQSQ t QSQHZ t QSVLD t DQSH t DQSL Note: Minimum data valid window can be expressed as MIN ( pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN 256Mb: x16, x32 2. CKL CK t CKDQS DQSQ t DQSQ -33 Min Max Min 3.3 4.0 0.45 0.55 0.45 ...
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... READ Burst CK# CK CMD RD NOP A ADDR BA0 DQSx DQSx# DVLD DQ Note: A/BAx: address A of bank x Dxy: data y to bank x RC: row cycle time RL: READ latency. pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN 256Mb: x16, x32 2.5V V EXT BA2 BA3 BA4 BA7 Q0a ...
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... CK CMD ADDR BA0 BA1 DQ DVLD DQSx DQSx# Note: A/BAx: address A of bank x Dxy: data y to bank x RD: READ RL: READ latency WL: WRITE latency. pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN 256Mb: x16, x32 2. NOP NOP NOP WR A BA1 Q0a Q0b NOP NOP NOP ...
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... CMD ADDR BA0 BA1 DVLD DQSx DQSx# Note: A/BAx: address A of bank x Dxy: data y to bank x RD: READ RL: READ latency WL: WRITE latency. pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN 256Mb: x16, x32 2. NOP NOP NOP NOP Q0a Q0b NOP NOP NOP NOP ...
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... ARFx Notes: 1. ACx: any command on bank x ARFx: auto refresh bank x ACy: any command on different bank configuration-dependent. Refer to Table 10 on page 16. pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN 256Mb: x16, x32 2.5V V EXT t RC. t REF), the entire memory must be refreshed. Figure 25 illus- BA DON’T CARE ...
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... The RLDRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling The JTAG Feature It is possible to operate the RLDRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (V are internally pulled up and may be unconnected. They may alternately be connected to V through a pull-up resistor ...
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... Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the RLDRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK ...
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... The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hard- wired into the RLDRAM and can be shifted out when the TAP controller is in the Shift- DR state. The ID register has a vendor code and other information described in Table 15 on page 33 ...
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... RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this RLDRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals into the RLDRAM and cannot preload the I/O buffers. The RLDRAM does not implement the 1149.1 com- mands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD ...
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... To guarantee that the boundary scan register will capture the correct value of a signal, the RLDRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time ( correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRE- LOAD instruction ...
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... Capture setup Hold Times TMS hold Capture hold t Notes and boundary scan register pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN 256Mb: x16, x32 2.5V V EXT ≤ +95°C; +1.7V ≤ V ≤ +1.95V refer to the setup and hold time requirements of latching data from the Micron Technology, Inc ...
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... TDO. This instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect RLDRAM operations. Places the bypass register between TDI and TDO. This operation does not affect RLDRAM operations. ...
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... U11 30 U11 31 T10 32 T10 33 T11 34 T11 35 R10 Notes: 1. Any unused pins that are in the order will read as a logic “0.” pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN 256Mb: x16, x32 2.5V V EXT Bit# FBGA Ball 36 R11 37 P11 38 P11 39 P10 40 P10 41 N11 ...
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... Isolated output buffer supply Reference voltage Notes: 1. All voltages referenced During normal operation Typically the value of V expected to track variations Peak to peak AC noise on V pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN 256Mb: x16, x32 2. × 0.1µF/device : 2 × 0.1µF/device : 0.1µF/device : 0.1µ ...
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... Input high (Logic 1) voltage Input low (Logic 0) voltage Input high (Logic 1) voltage Input low (Logic 0) voltage Figure 31: Output Test Conditions DQ pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN 256Mb: x16, x32 2.5V V Recommended DC Operation Ranges ≤ +1.95V unless otherwise noted DD Conditions Symbol V IH ...
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... Operating supply MIN, 8 bank cyclic access, current example half of address bits change every 2 clocks, continuous data pdf: 09005aef81121545/source: 09005aef810c0ffc 256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN 256Mb: x16, x32 2. MAX unless otherwise noted Conditions Symbol ...
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... Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. RLDRAM is a trademark of Infineon Technologies AG in various countries, and is used by Micron Technology, Inc. under license from Infineon. All other trademarks are the property of their respective owners. ...