K7N163645A-QC16 Samsung Semiconductor, K7N163645A-QC16 Datasheet
K7N163645A-QC16
Specifications of K7N163645A-QC16
Related parts for K7N163645A-QC16
K7N163645A-QC16 Summary of contents
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... K7N163645A K7N161845A 18Mb NtRAM 100 TQFP & 165FBGA with Pb & Pb-Free INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ...
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... K7N163645A K7N161845A Document Title 512Kx36 & 1Mx18-Bit Pipelined NtRAM Revision History Rev. No. History 0.0 1. Initial document. 0.1 1. Add JTAG Scan Order 0.2 1. Add x32 org and industrial temperature . 2. Add 165FBGA package 0.3 1. Speed bin merge. From K7N1636(32/18)49A to K7N1636(32/18)45A parameter change. tOH(min)/tLZC(min) from 0.8 to 1.5 at -25 tOH(min)/tLZC(min) from 1 ...
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... K7N163645A K7N161845A 16Mb NtRAM(Flow Through / Pipelined) Ordering Informa Org. Part Number K7M161825A-QC(I)65/75 1Mx18 K7N161801A-Q(F)C(I)25/20/16/13 K7N161845A-Q(F)C(I)25/20/16/13 K7M163625A-QC(I)65/75 512Kx36 K7N163601A-Q(F)C(I)25/20/16/13 K7N163645A-Q(F)C(I)25/20/16/13 512Kx36 & 1Mx18 Pipelined NtRAM tion Speed Mode VDD FT ; Access Time(ns) Pipelined ; Cycle Time(MHz) FlowThrough 3.3 6.5/7.5 ns Pipelined 3.3 250/200/167/133MHz Pipelined 2.5 ...
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... Unit The K7N163645A and K7N161845A are implemented with SAMSUNG′s high performance CMOS technology and is avail- 5.0 6.0 7.5 ns able in 100pin TQFP and 165FBGA packages. Multiple power 3 ...
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... LBO Burst Mode Control Note : A and A are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired 512Kx36 & 1Mx18 Pipelined NtRAM 100 Pin TQFP (20mm x 14mm) K7N163645A(512Kx36) TQFP PIN NO. SYMBOL 32,33,34,35,36,37, 45,46,47,48,49,50,81 82,83,84,99,100 V SS ...
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... K7N163645A K7N161845A PIN CONFIGURATION (TOP VIEW) N.C. 1 N. DDQ V 5 SSQ N.C. 6 N.C. 7 DQb 8 8 DQb SSQ V 11 DDQ DQb 12 6 DQb DQb 18 4 DQb DDQ V 21 SSQ DQb 22 2 DQb 23 1 DQb N. SSQ 27 V DDQ N.C. 28 N.C. 29 N.C. 30 PIN NAME ...
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... K7N163645A K7N161845A 165-PIN FBGA PACKAGE CONFIGURATIONS K7N163645A(512Kx36 CS1 CS2 C DQPc NC V DDQ D DQc DQc V DDQ E DQc DQc V DDQ F DQc DQc V DDQ G DQc DQc V DDQ DQd DQd V DDQ K DQd DQd V DDQ L DQd DQd V DDQ M DQd DQd V DDQ N DQPd NC V DDQ LBO NC A Note : * A and A are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired ...
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... K7N163645A K7N161845A 165-PIN FBGA PACKAGE CONFIGURATIONS K7N161845A(1Mx18 CS1 CS2 DDQ D NC DQb V DDQ E NC DQb V DDQ F NC DQb V DDQ G NC DQb V DDQ DQb NC V DDQ K DQb NC V DDQ L DQb NC V DDQ M DQb NC V DDQ N DQPb NC V DDQ LBO NC A Note : * A and A are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired ...
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... K7N163645A K7N161845A FUNCTION DESCRIPTION The K7N163645A and K7N161845A are NtRAM there is transition from Read to Write, or vice versa. All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges. All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV) ...
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... K7N163645A K7N161845A BEGIN READ READ BURST COMMAND DS READ WRITE BURST Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock(CLK) 512Kx36 & ...
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... K7N163645A K7N161845A TRUTH TABLES SYNCHRONOUS TRUTH TABLE ADV WE BWx Notes : 1. X means "Don′t Care". 2. The rising edge of clock is symbolized by (↑). 3. A continue deselect cycle can only be enterd if a deselect cycle is executed first. 4. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. ...
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... K7N163645A K7N161845A ASYNCHRONOUS TRUTH TABLE OPERATION ZZ Sleep Mode H L Read L Write L Deselected L ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on V Supply Relative Voltage on Any Other Pin Relative to V Power Dissipation Storage Temperature Operating Temperature Storage Temperature Range Under Bias *Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied ...
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... K7N163645A K7N161845A DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Input Leakage Current(except ZZ) Output Leakage Current Operating Current Standby Current Output Low Voltage Output High Voltage Input Low Voltage Input High Voltage Notes : 1. The above parameters are also guaranteed at industrial temperature range. 2. Reference AC Operating Conditions and Characteristics for input and timing. ...
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... K7N163645A K7N161845A Output Load(A) Dout Zo=50Ω AC TIMING CHARACTERISTICS =2.5V ±5 70° PARAMETER Cycle Time Clock Access Time Output Enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z ...
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... K7N163645A K7N161845A SLEEP MODE SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to I SLEEP MODE is dictated by the length of time the High state. After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE ...
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... K7N163645A K7N161845A IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control ...
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... K7N163645A K7N161845A SCAN REGISTER DEFINITION Part Instruction Register 512Kx36 3 bits 1Mx18 3 bits ID REGISTER DEFINITION Revision Number Part (31:28) 512Kx36 0000 1Mx18 0000 165FBGA BOUNDARY SCAN EXIT ORDER(x36 LBO 11P 10P A 9 10R A 10 11R A 11 11H ZZ 12 11N DQa 13 11M DQa ...
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... K7N163645A K7N161845A JTAG DC OPERATING CONDITIONS Parameter Power Supply Voltage Input High Level Input Low Level Output High Voltage Output Low Voltage NOTE : The input level of SRAM pin is to follow the SRAM DC specification 1. In Case of I/O Pins, the Max. V JTAG AC TEST CONDITIONS ...
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... K7N163645A K7N161845A 512Kx36 & 1Mx18 Pipelined NtRAM Rev. 3.0 November 2003 - ...
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... K7N163645A K7N161845A 512Kx36 & 1Mx18 Pipelined NtRAM Rev. 3.0 November 2003 - ...
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... K7N163645A K7N161845A 512Kx36 & 1Mx18 Pipelined NtRAM Rev. 3.0 November 2003 - ...
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... K7N163645A K7N161845A 512Kx36 & 1Mx18 Pipelined NtRAM Rev. 3.0 November 2003 - ...
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... K7N163645A K7N161845A 512Kx36 & 1Mx18 Pipelined NtRAM Rev. 3.0 November 2003 - ...
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... K7N163645A K7N161845A PACKAGE DIMENSIONS 100-TQFP-1420A #1 0.65 512Kx36 & 1Mx18 Pipelined NtRAM 22.00 ±0.30 20.00 ±0.20 (0.58) 0.30 ±0.10 0.10 MAX 1.40 0.05 MIN 0.50 ±0. Units ; millimeters/Inches ° 0~8 + 0.10 0.127 - 0.05 16.00 ±0.30 0.10 MAX 14.00 ±0.20 (0.83) 0.50 ±0.10 1.60 MAX ± ...
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... K7N163645A K7N161845A 165 FBGA PACKAGE DIMENSIONS 13mm x 15mm Body, 1.0mm Bump Pitch, 11x15 Ball Array C E Symbol Value Units 15 ± 0 ± 0.1 B 1.3 ± 0.1 C 0.35 ± 0.05 D 512Kx36 & 1Mx18 Pipelined NtRAM ∅ H Note Symbol Top View Side View D Bottom View ...