DSP56303PV100 Freescale Semiconductor, DSP56303PV100 Datasheet - Page 18

• Manufacturer Part Number: DSP56303PV100
• Manufacturer: Freescale Semiconductor

Specifications of DSP56303PV100

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

Signals/Connections
1.10 Serial Communication Interface (SCI)
The SCI provides a full duplex port for serial communication with other DSPs, microprocessors, or peripherals
such as modems.
1-14
RXD
PE0
TXD
PE1
SCLK
PE2
Notes:
Signal Name
1.
2.
3.
In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, the signal is tri-stated.
The Wait processing state does not affect the signal state.
All inputs are 5 V tolerant.
Input
Input or Output
Output
Input or Output
Input/Output
Input or Output
Type
Table 1-14.
State During
Ignored Input
Ignored Input
Ignored Input
Reset
DSP56303 Technical Data, Rev. 11
1,2
Serial Communication Interface
Serial Receive Data—Receives byte-oriented serial data and transfers it to the
SCI Receive Shift Register.
Port E 0—The default configuration following reset is GPIO input PE0. When
configured as PE0, signal direction is controlled through the Port E Direction
Register. The signal can be configured as an SCI signal RXD through the Port E
Control Register.
Serial Transmit Data—Transmits data from the SCI Transmit Data Register.
Port E 1—The default configuration following reset is GPIO input PE1. When
configured as PE1, signal direction is controlled through the Port E Direction
Register. The signal can be configured as an SCI signal TXD through the Port E
Control Register.
Serial Clock—Provides the input or output clock used by the transmitter and/or
the receiver.
Port E 2—The default configuration following reset is GPIO input PE2. When
configured as PE2, signal direction is controlled through the Port E Direction
Register. The signal can be configured as an SCI signal SCLK through the Port
E Control Register.
Signal Description
Freescale Semiconductor