FW21154AE Intel, FW21154AE Datasheet - Page 31

• Manufacturer Part Number: FW21154AE
• Manufacturer: Intel

Specifications of FW21154AE

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

14.
Table 34.
15.
21154 PCI-to-PCI Bridge Specification Update
Section 10.2, Secondary Clock Control, Table 34
This table has been re-arranged to indicate the gpio serial data format. It now appears as follows:
Section 10.2.1, Mask and Load Shift Timing Events for 66 MHz Operation
The following new section has been added:
The following list provides the timing sequence for 66 MHz operation for an example circuit as
shown in
GPIO Serial Data Format
1. The gpio<2> original coming from the 21154 does not provide 3ns setup time needed to
2. The shifted gpio<2> is delayed by ~9ns to provide ample setup time to enable the parallel of
3. Bit 15 input D6 of the shift register is pulled high, to Vcc.
4. Bit 14 input D7 is pulled high, to Vcc. These signals are not used internally in the 21154.
5. Bit 13 s_clk_o<9> is a feedback to the 21154 s_clk_o input. To enable s_clk_o<9> in all cases
6. Bit 12 s_clk_o<8> is disabled.
7. Bit 11 s_clk_o<7> is disabled.
8. Bit 10 s_clk_o<6> is disabled.
9. Bit 9 s_clk_o<5> is disabled.
provide the parallel load enable PE# of the 74F166.
the shift register connected to pin 15 of the 74F166.
the D5 input of the shift register is grounded, to Vss.
<15:14>
<7:6>
<5:4>
<3:2>
<1:0>
<13>
<12>
<10>
<11>
<9>
<8>
Bit
Figure 19
Reserved
21154 s_clk input
Device 8
Device 7
Device 6
Device 5
Device 4
Slot 3 PRSNT#<1:0> or device 3
Slot 2 PRSNT#<1:0> or device 2
Slot 1 PRSNT#<1:0> or device 1
Slot 0 PRSNT#<1:0> or device 0
and the timing diagram in
Description
Figure 21.
Documentation Changes
Intel Confidential31
s_clk_o Output
Not applicable
9
8
7
6
5
4
3
2
1
0