HD74LV373ATELL Renesas Electronics America, HD74LV373ATELL Datasheet

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HD74LV373ATELL

Manufacturer Part Number
HD74LV373ATELL
Description
Manufacturer
Renesas Electronics America
Type
D-Typer
Datasheet

Specifications of HD74LV373ATELL

Logic Family
LV
Number Of Bits
8
Number Of Elements
1
Latch Mode
Transparent
Polarity
Non-Inverting
Technology
CMOS
Output Type
3-State
Package Type
TSSOP
Propagation Delay Time
22ns
Operating Supply Voltage (typ)
2.5/3.3/5V
High Level Output Current
-16mA
Low Level Output Current
16mA
Operating Supply Voltage (min)
2V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
20
Lead Free Status / Rohs Status
Not Compliant
To our customers,
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
On April 1
st
, 2010, NEC Electronics Corporation merged with Renesas Technology
Renesas Electronics website:
Old Company Name in Catalogs and Other Documents
http://www.renesas.com
April 1
Renesas Electronics Corporation
st
, 2010

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HD74LV373ATELL Summary of contents

Page 1

To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

Page 2

All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

Page 3

... V (@V OH Output current ±8 mA (@V CC Ordering Information Part Name Package Type HD74LV373AFPEL SOP–20 pin (JEITA) HD74LV373ARPEL SOP–20 pin (JEDEC) HD74LV373ATELL TSSOP–20 pin Note: Please consult the sales office for the above package availability. Function Table Inputs ...

Page 4

HD74LV373A Pin Arrangement Absolute Maximum Ratings Item Supply voltage range 1 Input voltage range Output voltage range* Input clamp current Output clamp current Continuous output current Continuous current through V or GND CC Maximum power dissipation at 3 ...

Page 5

HD74LV373A Recommended Operating Conditions Item Supply voltage range Input voltage range Output voltage range Output current Input transition rise or fall rate Operating free-air temperature Note: Unused or floating inputs must be held high or low. Logic Diagram Rev.2.00 Jun. ...

Page 6

HD74LV373A DC Electrical Characteristics Item Symbol Input voltage Output voltage Input current I IN Off-state output I OZ current Quiescent supply I CC current Output leakage I OFF current Input capacitance C ...

Page 7

HD74LV373A Switching Characteristics Ta = 25°C Item Symbol Min Propagation t — PLH delay time t — PHL — — Enable time t — — ZL Disable time t — — LZ Setup time t 4.5 ...

Page 8

HD74LV373A Output-skew Characteristics Item Symbol Output skew t sk (O) Note: Skew between any outputs of the same package switching in the same direction. This parameter is warranted but not production tested. Operating Characteristics Item Power dissipation capacitance Noise Characteristics ...

Page 9

HD74LV373A Waveform 1 Input LE Input D Output Q Waveform Input LE 10% Input D 10% Output Q Waveform 3 Input LE Input D Rev.2.00 Jun. 25, 2004 page 90% ...

Page 10

HD74LV373A Waveform 4 90% Input OE 50%V 10% Waveform A Waveform B Notes ns Input waveform: PRR 3. Waveform A is for an output with internal conditions such that the output is low except ...

Page 11

HD74LV373A Package Dimensions 20 1 0.80 Max 1.27 *0.40 ± 0.06 *Pd plating 13.2 Max 20 1 0.935 Max 1.27 *0.40 ± 0.06 *Ni/Pd/Au plating Rev.2.00 Jun. 25, 2004 page 12.6 13 Max 11 10 0.15 0.12 ...

Page 12

HD74LV373A 6.50 6.80 Max 20 1 *0.20 ± 0.05 0.65 Max *Pd plating Rev.2.00 Jun. 25, 2004 page 0.65 0.13 M 6.40 ± 0.20 0.10 Package Code JEDEC JEITA Mass (reference value January, ...

Page 13

Sales Strategic Planning Div. Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble ...

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