W83L518D Nuvoton Technology Corporation of America, W83L518D Datasheet - Page 13

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W83L518D

Manufacturer Part Number
W83L518D
Description
Manufacturer
Nuvoton Technology Corporation of America
Datasheet

Specifications of W83L518D

Lead Free Status / Rohs Status
Supplier Unconfirmed

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7. POWER SEQUENCE
Note:
1.2VLDT_PG
ALLPWR_OK
V
RUN_MISC
TT
1.25VREF
1. When at power up sequence, the delay time between adjacent power planes is 5ms after the
2. When at power down sequence, the delay time between adjacent power planes is 20ms
3. After 1.2VLDT_PG=H and delay 20ms, the ALLPWR_OK will be High(ALLPWR_OK=H).
4. All “LUV” detect is enabled after the power plane have power-good.
V
RSMRST#
2.5VDDA
V
1.2VLDT
PSOUT#
&V
CORE
PWROK
CORE
PSIN#
5VSB
VCC
S3#
S5#
AGP
RAM
previous power plane is power-good.
after the previous power plane is power-down.
_EN
_PG
&
4.3
82mS
W83304D power sequence(RUN_MISC default)
- 13 -
W83304D/W83304G
Publication Release Date: April, 2006
Revision 0.51
3.7

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