5962-9176402M3A Analog Devices Inc, 5962-9176402M3A Datasheet - Page 7

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5962-9176402M3A

Manufacturer Part Number
5962-9176402M3A
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of 5962-9176402M3A

Number Of Channels
4
Resolution
12b
Conversion Rate
167KSPS
Interface Type
Parallel
Single Supply Voltage (typ)
5V
Dual Supply Voltage (typ)
±15V
Settling Time
10us
Architecture
R-2R
Power Supply Requirement
Single/Dual
Output Type
Voltage
Integral Nonlinearity Error
±1.5LSB
Single Supply Voltage (min)
4.75V
Single Supply Voltage (max)
5.25V
Dual Supply Voltage (min)
±14.25V
Dual Supply Voltage (max)
±15.75V
Operating Temp Range
-55C to 125C
Operating Temperature Classification
Military
Mounting
Surface Mount
Pin Count
28
Package Type
LCC
Lead Free Status / Rohs Status
Not Compliant
ABSOLUTE MAXIMUM RATINGS
T
Table 3.
Parameter
V
V
V
V
V
V
Current into Any V
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Operating Temperature Range
Junction Temperature
Storage Temperature Range
Power Dissipation Package
Lead Temperature
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
SS
SS
LOGIC
SS
REFH
REFH
A
EP, FP, FPC
AT, BT, BTC
Soldering
= +25°C, unless otherwise noted.
to V
to V
to V
to V
to V
to DGND
DD
LOGIC
REFL
DD
REFL
SS
pin
Rating
−0.3 V, +33.0 V
−0.3 V, +33.0 V
−0.3 V, +7.0 V
−0.3 V, +V
+2.0 V, +33.0 V
+2.0 V, V
±15 mA
−0.3 V, V
−0.3 V, +7.0 V
−40°C to +85°C
−55°C to +125°C
150°C
−65°C to +150°C
1000 mW
JEDEC Industry Standard
J-STD-020
SS
LOGIC
SS
− V
− 2.0 V
+ 0.3 V
DD
Rev. F | Page 7 of 20
THERMAL RESISTANCE
θ
device in socket.
Table 4. Thermal Resistance
Package Type
28-Lead Plastic DIP (PDIP)
28-Terminal Ceramic Leadless Chip Carrier (LLC)
28-Lead Plastic Leaded Chip Carrier (PLLC)
28-Lead Ceramic Dual In-Line Package (CERDIP)
ESD CAUTION
JA
is specified for the worst-case mounting conditions, that is, a
DAC8412/DAC8413
θ
48
70
63
51
JA
θ
22
28
25
9
JC
Unit
°C/W
°C/W
°C/W
°C/W

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