AM29LV320DT90WMF AMD (ADVANCED MICRO DEVICES), AM29LV320DT90WMF Datasheet - Page 16

• Manufacturer Part Number: AM29LV320DT90WMF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29LV320DT90WMF

• Lead Free Status / Rohs Status: Compliant

7.6
7.7
7.8
7.9
14
Standby Mode
Automatic Sleep Mode
RESET#: Hardware Reset Pin
Output Disable Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,
independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V
(Note that this is a more restricted voltage range than V
V
requires standard access time (t
before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation
is completed.
In the
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for t
WE#, and OE# control signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the system. I
Characteristics on page 46
The RESET# pin provides a hardware method of resetting the device to reading array data. When the system
drives the RESET# pin to V
progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state machine to reading array data. The operation that was
interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure
data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at V
draws CMOS standby current (I
will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the
internal reset operation is complete, which requires a time of t
system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not executing (RY/BY# pin is 1), the reset operation is
completed within a time of t
RESET# pin returns to V
Refer to
diagram.
When the OE# input is at V
impedance state.
CC
± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device
Parameter
DC Characteristics
t
ASM
AC Characteristics on page 49
IH
table, I
.
IL
READY
IH
represents the automatic sleep mode current specification.
, output from the device is disabled. The output pins are placed in the high
for at least a period of t
CC4
CE
CC3
Table 7.2 Automatic Sleep Mode Timing
(not during Embedded Algorithms). The system can read data t
) for read access when the device is in either of these standby modes,
Automatic Sleep Mode
). If RESET# is held at V
and I
Description
S29AL032D
for RESET# parameters and to
CC4
D a t a
ASM
represents the standby current specification.
. The automatic sleep mode is independent of the CE#,
RP
, the device immediately terminates any operation in
S h e e t
IH
.) If CE# and RESET# are held at V
IL
READY
but not within V
(during Embedded Algorithms). The
Figure 17.2 on page 50
t
ACC
Max.
+30
SS
S29AL032D_00_A8 November 2, 2006
±0.3 V, the standby current
SS
±0.3 V, the device
CC4
IH
, but not within
in
for the timing
CC
Unit
RH
ns
DC
± 0.3 V.
after the