TA8030S Toshiba, TA8030S Datasheet - Page 4

• Manufacturer Part Number: TA8030S
• Manufacturer: Toshiba

Specifications of TA8030S

• Number Of Elements: 2
• Battery Backup Switching: No
• Watchdog Timer: Yes
• Chip Enable Signals: No
• Manual Reset: No
• Package Type: SIP
• Operating Supply Voltage (max): 17V
• Reset Threshold Voltage (max): 4.5/4.9V
• Reset Threshold Voltage (min): 4/4.4V
• Power Dissipation: 300mW
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Power Fail Detection: No
• Mounting: Through Hole
• Pin Count: 7
• Supply Current: 4.5mA
• Lead Free Status / Rohs Status: Not Compliant

FUNCTIONAL DESCRIPTION
About reset timer operation (See the timing chart)
The following explains the TA8030S/F's voltage monitoring and reset timer operations and how to use these
functions.
(1) Voltage monitoring function
(2) Voltage monitoring function
(3) Power-on reset timer function
(4) Watchdog timer function
The power input V
4.25V after the IC is powered on, the power-on reset timer starts operating from that point in time. When
the IC is powered off and V
the voltage drops below 40% of V
reset signal is output in the same way as described above, and when V
power-on reset timer starts operating from that point in time.
The reset signal is forwarded to the
The
4.48V. This function only monitors the voltage operating independently of Voltage monitoring function (1)
and the reset timer function. Since when the voltage drops the
reset signal is output from
Also, this voltage detection has 3
inadvertently by minute noise. (For td2, refer to AC Electrical Characteristics.)
The device is held in a reset state for a predetermined time until the 5V constant voltage stabilizes at
power-on and until the oscillating clock of the CPU, etc. stabilizes before being freed from the reset state.
This time can be set to any desired duration by using the appropriate resistor and capacitor values
connected external to the TC pin.
When the V
voltage exceeds 2V, the reset signal is inverted to deactivate the reset.
The WD pin between the CPU system and this IC is connected with an differential circuit. This is to ensure
that when a failure occurs in the CPU system, a low signal is input to the WD pin no matter whether the
clock output has stopped in the high or the low state. When the WD pin is fixed high, the watchdog timer
stops operating.
If only the power-on reset timer is needed in your system, connect the WD pin to
RST
2
pin outputs a high when the V
CC
voltage exceeds 4.25V, the system starts charging the capacitor and when this charging
CC
pin of this IC also serves as a voltage detection pin. When the V
CC
RST
drops below 4.25V, TC starts discharging and a reset signal is output when
1
CC
μ
, this function can be used to inhibit writing to memory.
(1)
(2)
. Also, if V
s of response delay, td2, to prevent a reset from being generated
RST
1
CC
pin.
voltage rises above 4.65V and outputs a low when it falls below
CC
4
goes down for some reason during normal operation, a
RST
2
CC
output is inverted before a system
is up again and exceeds 4.25V, the
RST
1
CC
.
voltage exceeds
TA8030S/F
2002-02-27