LM81CIMTX-3 National Semiconductor, LM81CIMTX-3 Datasheet - Page 13

• Manufacturer Part Number: LM81CIMTX-3
• Manufacturer: National Semiconductor

Specifications of LM81CIMTX-3

• Monitored Voltage 1 (typ): 2.5/3.3/5/12V
• Battery Backup Switching: No
• Watchdog Timer: Yes
• Chip Enable Signals: No
• Manual Reset: No
• Package Type: TSSOP
• Operating Supply Voltage (min): 2.8V
• Operating Supply Voltage (max): 3.8V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Power Fail Detection: No
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / Rohs Status: Not Compliant

Functional Description
2.2 Serial Bus Interface
The Serial Bus control lines consist of the SMBData (serial
data), SMBCLK (serial clock) and A0-A1 (address) pins. The
LM81 can operate only as a slave. The SMBCLK line only
controls the serial interface, all other clock functions within
LM81 such as the ADC and fan counters are done with a
separate asynchronous internal clock.
When using the Serial Bus Interface a write will always
consist of the LM81 Serial Bus Interface Address byte, fol-
lowed by the Internal Address Register byte, then the data
byte. There are two cases for a read:
1. If the Internal Address Register is known to already be at
2. If the Internal Address Register value is unknown, or if it
the desired Address, simply read the LM81 with the
Serial Bus Interface Address byte, followed by the data
byte read from the LM81.
is not the desired value, write to the LM81 with the Serial
(c) Serial Bus Read from a Register with the Internal Address Register Preset to Desired Location
(a) Serial Bus Write to the Internal Address Register followed by the Data Byte
(b) Serial Bus Write to the Internal Address Register Only
(Continued)
FIGURE 5. Serial Bus Timing
13
The default Serial Bus address of the LM81 is set to 010
11(A1)(A0). All bits, except for A0 and A1, can be changed by
writing to the Serial Bus address register. A0 and A1 will
always reflect the state of the A0 and A1 input pins.
All of these communications are depicted in the Serial Bus
Interface Timing Diagrams as shown in Figure 5 .
Serial Bus Timeout can be initiated by holding the SMBCLK
and/or SMBData lines low for greater than t
max). Serial Bus Timeout resets the serial bus interface
circuitry to the idle state and readies the LM81 for a new
serial bus communication.
Bus Interface Address byte, followed by the Internal
Address Register byte. Then restart the Serial Commu-
nication with a Read consisting of the Serial Bus Inter-
face Address byte, followed by the data byte read from
the LM81.
DS100072-8
DS100072-10
DS100072-9
TIMEOUT
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(35 ms