K6T1008C2E-GB70 Samsung Semiconductor, K6T1008C2E-GB70 Datasheet - Page 8

• Manufacturer Part Number: K6T1008C2E-GB70
• Manufacturer: Samsung Semiconductor

Specifications of K6T1008C2E-GB70

• Density: 1Mb
• Access Time (max): 70ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 17b
• Package Type: SOP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 50mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Word Size: 8b
• Number Of Words: 128K
• Lead Free Status / Rohs Status: Not Compliant

DATA RETENTION WAVE FORM
K6T1008C2E Family
CS
CS
TIMING WAVEFORM OF WRITE CYCLE(3)
1
V
4.5V
2.2V
V
CS
GND
2
V
4.5V
CS
V
0.4V
GND
Address
CS
CS
WE
Data in
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS
2. t
3. t
4. t
CC
DR
CC
DR
controlled
controlled
CS
t
in case a write ends as CS
WP
CW
AS
WR
1
2
1
2
2
is measured from the address valid to the beginning of write.
is measured from the begining of write to the end of write.
is measured from the CS
is measured from the end of write to the address change. t
going high and WE going low: A write end at the earliest transition among CS
2
going to low.
1
going low or CS
High-Z
t
SDR
t
t
SDR
AS(3)
1
, a high CS
2
going high to the end of write.
(CS
2
Controlled)
2
and a low WE. A write begins at the latest transition among CS
Data Retention Mode
WR
Data Retention Mode
8
t
applied in case a write ends as CS
AW
CS V
t
t
WC
CS
CW(2)
t
CW(2)
2
CC
t
WP(1)
0.2V
- 0.2V
1
t
DW
going high, CS
Data Valid
t
WR(4)
t
DH
2
1
going low and WE going high,
or WE going high t
t
RDR
High-Z
t
RDR
CMOS SRAM
WR2
1
goes low,
Revision 4.0
applied
May 2002