CAT24WC04JI-TE13 ON Semiconductor, CAT24WC04JI-TE13 Datasheet - Page 4

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CAT24WC04JI-TE13

Manufacturer Part Number
CAT24WC04JI-TE13
Description
Manufacturer
ON Semiconductor
Datasheet

Specifications of CAT24WC04JI-TE13

Density
4Kb
Interface Type
Serial (I2C)
Organization
512x8
Access Time (max)
3.5us
Frequency (max)
100KHz
Write Protection
Yes
Data Retention
100Year
Operating Supply Voltage (typ)
3.3/5V
Package Type
SOIC N
Operating Temp Range
-40C to 85C
Supply Current
3mA
Operating Supply Voltage (min)
2.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
8
Lead Free Status / Rohs Status
Not Compliant

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CAT24WC01/02/04/08/16
FUNCTIONAL DESCRIPTION
The CAT24WC01/02/04/08/16 supports the I
data transmission protocol. This Inter-Integrated Circuit
Bus protocol defines any device that sends data to the
bus to be a transmitter and any device receiving data to
be a receiver. Data transfer is controlled by the Master
device which generates the serial clock and all START
and STOP conditions for bus access. The CAT24WC01/
02/04/08/16 operates as a Slave device. Both the Mas-
ter and Slave devices can operate as either transmitter
or receiver, but the Master device controls which mode
is activated. A maximum of 8 devices (CAT24WC01 and
CAT24WC02), 4 devices (CAT24WC04), 2 devices
(CAT24WC08) and 1 device (CAT24WC16) may be
connected to the bus as determined by the device
address inputs A0, A1, and A2.
Figure 1. Bus Timing
Figure 2. Write Cycle Timing
Figure 3. Start/Stop Timing
Doc. No. 1022, Rev. O
SDA OUT
SDA IN
SCL
SCL
SDA
t SU:STA
SDA
SCL
t F
8TH BIT
BYTE n
t HD:STA
t LOW
START BIT
t AA
ACK
t HD:DAT
t HIGH
2
C Bus
t LOW
STOP
CONDITION
4
t DH
PIN DESCRIPTIONS
SCL: Serial Clock
The CAT24WC01/02/04/08/16 serial clock input pin is
used to clock all data transfers into or out of the device.
This is an input pin.
SDA: Serial Data/Address
The CAT24WC01/02/04/08/16 bidirectional serial data/
address pin is used to transfer data into and out of the
device. The SDA pin is an open drain output and can be
wire-ORed with other open drain or open collector
outputs.
A0, A1, A2: Device Address Inputs
These inputs set device address when cascading mul-
tiple devices. When these pins are left floating the
default values are zeros.
A maximum of eight devices can be cascaded when
t SU:DAT
t R
t WR
START
CONDITION
STOP BIT
Characteristics subject to change without notice
t SU:STO
t BUF
© Catalyst Semiconductor, Inc.
ADDRESS
5020 FHD F03
5020 FHD F04
5020 FHD F05

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