PI6C185-01LX Pericom Semiconductor, PI6C185-01LX Datasheet - Page 5

PI6C185-01LX

Manufacturer Part Number
PI6C185-01LX
Description
Manufacturer
Pericom Semiconductor
Datasheet

Specifications of PI6C185-01LX

Number Of Outputs
5
Operating Supply Voltage (max)
3.465V
Operating Temp Range
0C to 70C
Propagation Delay Time
5.5ns
Operating Supply Voltage (min)
3.135V
Mounting
Surface Mount
Pin Count
16
Operating Supply Voltage (typ)
3.3V
Package Type
TSSOP
Duty Cycle
55%
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
Minimum and Maximum Expected Capacitive Loads
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load.
2. Minimum rise/fall times are guaranteed at minimum specified load.
3. Rise/fall times are specified with pure capacitive load as shown.
Design Guidelines to Reduce EMI
1. Place R
2. Minimize the number of “vias” of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing
4. Position clock signals away from signals that go to any cables or any external connectors.
S
C
D
Testing is done with an additional 500Ω resistor in parallel.
value for CI is 10 pF. R
and fall time are still within the specified values.
clock traces from plane to plane (refer to rule #2).
o l
R
A
k c
M
08-0298
S
M
series resistors and CI capacitors as close as possible to the respective clock pins. Typical
n i
0 2
L
o
d a
M
x a
Waveform
0 3
S
L
Series resistor value can be increased to reduce EMI provided that the rise
o
d a
Waveform
Clocking
Interface
Input
U
(TTL)
F p
3.3V
Output
n
s t i
S
D
2.4
1.5
0.4
R
A
M
t
plh
I D
M
t
SDRISE
Figure 1. Clock Waveforms
M
N
1.5V
t o
p S
s e
c e
c i f i
tSDKH
Output
Buffer
i t a
1.5V
n o
5
tSDKP
t
SDFALL
Test Load
tSDKL
Test
Point
1.5V
1.5V
t
Precision 1-5 Clock Buffer
phl
PI6C185-01
PS8318F
11/13/08
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5

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