UPD75P3216GT Renesas Electronics America, UPD75P3216GT Datasheet - Page 41

• Manufacturer Part Number: UPD75P3216GT
• Manufacturer: Renesas Electronics America

Specifications of UPD75P3216GT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS
Notes 1.
Data Retention Timing (STOP Mode Release by RESET)
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
RESET
V
Standby Release Signal
(Interrupt Request)
Release signal set time
Oscillation stabilization
wait time
DD
V
DD
STOP Instruction Execution
2.
Parameter
STOP Instruction Execution
Note 1
BTM3
The oscillation stabillization wait time is the time during which the CPU operation is stopped to prevent
unstable operation at the oscillation start.
Depends on the basic interval timer mode register (BTM) settings (See the table below).
—
—
—
—
BTM2
0
0
1
1
Symbol
t
t
SREL
WAIT
BTM1
0
1
0
1
Release by RESET
Release by interrupt
BTM0
0
1
1
1
V
DDDR
Data Retention Mode
V
Data Sheet U10241EJ1V1DS
DDDR
When fx = 4.19-MHz operation
2
2
2
2
STOP Mode
Data Retention Mode
STOP Mode
20
17
15
13
/fx (approx. 250 ms)
/fx (approx. 31.3 ms)
/fx (approx. 7.81 ms)
/fx (approx. 1.95 ms)
Test Conditions
Wait Time
Internal Reset Operation
t
SREL
2
2
2
2
When fx = 6.0-MHz operation
20
17
15
13
t
SREL
/fx (approx. 175 ms)
/fx (approx. 21.8 ms)
/fx (approx. 5.46 ms)
/fx (approx. 1.37 ms)
HALT Mode
HALT Mode
MIN.
t
WAIT
0
t
WAIT
(T
Note 2
µ PD75P3216
TYP.
2
A
15
/f
= –40 to +85 ˚C)
X
Operating Mode
MAX.
Operating Mode
Unit
ms
ms
µ s
39