PI6CV857A Pericom Semiconductor, PI6CV857A Datasheet

PI6CV857A

Manufacturer Part Number

PI6CV857A

Description

Manufacturer

Pericom Semiconductor

Type

Zero Delay PLL Clock Driverr

Datasheet

1.PI6CV857A.pdf (10 pages)

Specifications of PI6CV857A

Number Of Elements

Pll Input Freq (min)

60MHz

Pll Input Freq (max)

170MHz

Operating Supply Voltage (typ)

2.5V

Operating Temp Range

0C to 70C

Package Type

TSSOP

Output Frequency Range

60 to 170MHz

Operating Supply Voltage (min)

2.3V

Operating Supply Voltage (max)

2.7V

Operating Temperature Classification

Commercial

Pin Count

04+

Lead Free Status / Rohs Status

Not Compliant

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Block Diagram/Pin Configuration

Product Features

• PLL clock distribution optimized for Double Data Rate

• Distributes one differential clock input pair to ten differential

• Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2

• Input PWRDWN: LVCMOS

• Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2

• External feedback pins (FBIN,FBIN) are used to

• Operates at AV

• Packaging: (Pb-free & Green available)

SDRAM applications.

clock output pairs.

synchronize the outputs to the clock input.

and V

— Plastic 48-pin TSSOP (A)

PWRDWN

AV DD

FBIN

CLK

08-0298

DDQ

= 2.5V for differential output drivers

= 2.5V for core circuit and internal PLL,

Powerdown

and Test

Logic

PLL

FBOUT

Product Description

PI6CV857 PLL clock device is developed for registered DDR DIMM

applications This PLL Clock Buffer is designed for 2.5 V

Package options include plastic Thin Shrink Small-Outline Package

(TSSOP).The device is a zero delay buffer that distributes a differ-

ential clock input pair (CLK, CLK) to ten differential pairs of clock

outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock

outputs (FBOUT,FBOUT) . The clock outputs are controlled by the

input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), the 2.5V

LVCMOS input (PWRDWN) and the Analog Power input (AV

When input PWRDWN is low while power is applied, the input

receivers are disabled, the PLL is turned off and the differential clock

outputs are 3-stated. When the AV

turned off and bypassed for test purposes.

When the input frequency falls below a suggested detection fre-

quency that is below the operating frequency of the PLL, the device

will enter a low power mode. An input frequency detection circuit will

detect the low frequency condition and perform the same low power

features as when the PWRDWN input is low.

The PLL in the PI6CV857 clock driver uses input clocks (CLK, CLK)

and feedback clocks (FBIN,FBIN) to provide high-performance, low-

skew, low-jitter output differential clocks (Y[0:9], Y[0:9]). PI6CV857

is also able to track Spread Spectrum Clocking for reduced EMI.

operation and differential data input and output levels.

A G N D

V D D Q

AV D D

V D D Q

G N D

C L K

2.5V DDR-SDRAM Memory

48-Pin

PLL Clock Driver for

is strapped low, the PLL is

G N D

V D D Q

G N D

V D D Q

P W R D W N

FBIN

V D D Q

F B O U T

G N D

V D D Q

G N D

PI6CV857

PS8464F

DDQ

and 2.5V

11/06/08

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PI6CV857A Summary of contents

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... Ordering Information Pericom Semiconductor Corporation • 1-800-435-2336 • http://www.pericom.com 08-0298 .236 .244 12.4 12.6 See Note 3 .047 1.20 Max .002 .007 .0197 .006 .010 BSC 0.05 0.50 0.17 0.15 0.27 Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335 • ...

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