CY7C67300-100AI Cypress Semiconductor Corp, CY7C67300-100AI Datasheet - Page 34

• Manufacturer Part Number: CY7C67300-100AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C67300-100AI

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: TQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

Host n Device Address Register [W]
■
■
Table 56. Host n Device Address Register
Register Description
The Host n Device Address register is a write only register that
contains the USB Device Address that the host wants to commu-
nicate with.
Host n Interrupt Enable Register [R/W]
■
■
Table 57. Host n Interrupt Enable Register
Register Description
The Host n Interrupt Enable register enables control over host
related interrupts.
In this register a bit set to ‘1’ enables the corresponding interrupt
while ‘0’ disables the interrupt.
VBUS Interrupt Enable (Bit 15)
The VBUS Interrupt Enable bit enables or disables the OTG
VBUS interrupt. When enabled this interrupt triggers on both the
rising and falling edge of VBUS at the 4.4V status (only
supported in Port 1A). This bit is only available for Host 1 and is
a reserved bit in Host 2.
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Host 1 Device Address Register 0xC088
Host 2 Device Address Register 0xC0A8
Host 1 Interrupt Enable Register 0xC08C
Host 2 Interrupt Enable Register 0xC0AC
Wake Interrupt
...Reserved
Interrupt
Enable
Enable
VBUS
Port B
R/W
R/W
15
15
0
7
0
0
7
0
-
-
Wake Interrupt
ID Interrupt
Enable
Enable
Port A
R/W
R/W
14
W
14
0
6
0
-
0
6
0
Port B Connect
Interrupt
Change
Enable
13
R/W
W
13
0
5
0
-
0
-
5
0
Port A Connect
Interrupt
Change
Enable
12
W
12
0
4
0
R/W
-
0
-
4
0
Reserved...
Reserved
Address (Bits [6:0])
The Address field contains the value of the USB address for the
next device that the host is going to communicate with. This
value must be written by firmware.
Reserved
Write all reserved bits with ’0’.
1: Enable VBUS interrupt
0: Disable VBUS interrupt
ID Interrupt Enable (Bit 14)
The ID Interrupt Enable bit enables or disables the OTG ID
interrupt. When enabled this interrupt triggers on both the rising
and falling edge of the OTG ID pin (only supported in Port 1A).
This bit is only available for Host 1 and is a reserved bit in Host 2.
1: Enable ID interrupt
0: Disable ID interrupt
Address
11
W
11
3
0
0
-
0
-
3
0
-
Reserved
10
W
10
2
0
2
0
0
-
-
0
-
SOF/EOP
Interrupt
Enable
R/W
W
1
0
1
0
9
0
-
9
0
-
CY7C67300
Reserved
Interrupt
Enable
Done
Page 34 of 99
R/W
W
0
0
0
0
8
0
-
8
0
-
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