CY7C1361B-100AI Cypress Semiconductor Corp, CY7C1361B-100AI Datasheet - Page 27

• Manufacturer Part Number: CY7C1361B-100AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1361B-100AI

• Density: 9Mb
• Access Time (max): 8.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 180mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 256K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05302 Rev. *B
Timing Diagrams
Write Cycle Timing
Notes:
22. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
Data Out (Q)
Data in (D)
ADDRESS
BWE,
BW
ADSP
ADSC
GW
CE
ADV
CLK
OE
X
BURST READ
High-Z
t ADS
t CES
[21, 22]
t AS
A1
(continued)
t ADH
t CEH
t
t AH
t
CH
OEHZ
Byte write signals are ignored for first cycle when
ADSP initiates burst
t CYC
t ADS
t
CL
Single WRITE
t
DS
D(A1)
t ADH
t
DH
A2
D(A2)
DON’T CARE
D(A2 + 1)
t
WES
BURST WRITE
t
WEH
D(A2 + 1)
UNDEFINED
ADV suspends burst
D(A2 + 2)
X
LOW.
ADSC extends burst
D(A2 + 3)
t ADS
A3
D(A3)
t ADH
t ADVS
Extended BURST WRITE
t WES
D(A3 + 1)
t ADVH
t WEH
D(A3 + 2)
CY7C1361B
CY7C1363B
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