CY7C1360A-225AJC Cypress Semiconductor Corp, CY7C1360A-225AJC Datasheet
CY7C1360A-225AJC
Specifications of CY7C1360A-225AJC
Related parts for CY7C1360A-225AJC
CY7C1360A-225AJC Summary of contents
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... JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation. The TA package version does not offer the JTAG capability. The CY7C1360A and CY7C1362A operate from a +3.3V power supply. All inputs and outputs are LVTTL-compatible. 7C1360A-225 7C1360A-200 ...
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... Address Register OUTPUT REGISTER CLR D Q Binary Counter & Logic [1] BYTE b WRITE D Q BYTE a WRITE D Q ENABLE Input Register Address Register OUTPUT REGISTER D Q CLR Binary Counter & Logic CY7C1360A CY7C1362A DQa,DQb DQa, DQb, DQc, DQd DQc,DQd DQa, DQb, DQa,DQb Page ...
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... DQa DQb 18 DQa 63 DQb 19 DQa CCQ 61 CCQ DQb 22 DQa 59 DQb 23 DQa 58 DQb CCQ 54 DDQ CY7C1360A CY7C1362A DQb 80 DQb 79 DQb CCQ DQb DQb 74 DQb 73 DQb CCQ DQb 69 DQb 100-pin TQFP Version DQa 63 DQa CCQ DQa 59 DQa 58 DQa 57 DQa CCQ DQa 53 DQa 52 DQa ...
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... N DQd P DQd CCQ CCQ DQb CCQ DQb J V CCQ DQb M V CCQ N DQb CCQ Document #: 38-05258 Rev. *A CY7C1360A 256K × 36 119-ball BGA Top ADSP CE A ADSC DQc DQc DQc DQc BWc ADV DQc DQd V CLK SS DQd BWd NC DQd V BWE SS DQd V A1 ...
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... Linear Burst HIGH on this pin selects Interleaved Burst. ZZ Input- Sleep: This active HIGH input puts the device in low Asynchronous power consumption standby mode. For normal operation, this input has to be either LOW or NC (No Connect). CY7C1360A CY7C1362A Description Page ...
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... All synchronous inputs must meet set-up and hold times around the clock’s rising edge. CE Input- Chip Enable: This active LOW input is used to enable the Synchronous device and to gate ADSP. CE Input- Chip Enable: This active HIGH input is used to enable the 2 Synchronous device. CY7C1360A CY7C1362A Description Description Page ...
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... TA/A package version. V Supply Core power supply: +3.3V –5% and +10 Ground Ground: GND I/O Power Power Supply for the I/O circuitry CCQ Supply NC – No Connect: These signals are not internally connected. User can leave it floating or connect CY7C1360A CY7C1362A Description Page ...
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... Bytes not selected during a byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1360A/CY7C1362A is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers ...
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... CE CE ADSP ADSC ADV CY7C1360A CY7C1362A Second Third Fourth Address Address Address (internal) (internal) (internal [1:0] [ Hi-Z Read Hi-Z Read Read Hi-Z Read Read Hi-Z Read Read Hi-Z Read Read Hi-Z Write Hi-Z Write Hi-Z Write Hi-Z Write ...
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... Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs, ADSP, and ADSC must remain inactive for the duration of t Description Test Conditions ZZ > > < 0.2V CY7C1360A CY7C1362A BWc BWb ...
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... The first column defines the bit’s position in the boundary scan register. The MSB of the register is connected to TDI, and LSB is connected to TDO. The second column is the signal name, the third column is the TQFP pin number, and the fourth column is the BGA bump number. CY7C1360A CY7C1362A ) ...
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... TAP controller is in the Shift-DR state, the bypass register is placed between TDI and TDO. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Reserved Do not use these instructions. They are reserved for future use. CY7C1360A CY7C1362A plus t ). The CS CH Page ...
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... The “0”/”1” next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05258 Rev SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- Figure 1. TAP Controller State Diagram CY7C1360A CY7C1362A 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- [11] ...
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... I = 100 A OHC [13 8.0 mA OLT [13 8.0 mA OHT /2; undershoot: V (AC) < – 0.5V for t < t KHKH IL KHKH must not exceed V . Control input signals (such as R/W, ADV/LD, etc.) may not have pulse widths less than CC CY7C1360A CY7C1362A 0 Selection Circuitry [12] Min. Max. 2 0.3 CC –0.3 0.8 – ...
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... TEST DATA IN (TDI) TEST DATA OUT (TDO) Document #: 38-05258 Rev. *A [16, 17] Over the Operating Range Description THTL THTH t t MVTH THMX t DVTH t THDX t TLQV t TLQX CY7C1360A CY7C1362A Min. Max ALL INPUT PULSES 3.0V 1.5V 1.5 ns 1.5 ns (b) t TLTH Page Unit ...
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... Do not use these instructions; they are reserved for future use. 110 Do not use these instructions; they are reserved for future use. 111 Places the bypass register between TDI and TDO. This instruction does not affect device operations. CY7C1360A CY7C1362A Description Description Page ...
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... CY7C1360A CY7C1362A (continued) Signal Name TQFP Bump BWa 93 5L BWb 94 5G BWc 95 3G BWd 100 2A DQc 1 2D DQc 2 1E DQc 3 2F DQc 6 1G DQc 7 2H DQc 8 1D DQc 9 2E DQc 12 2G DQc DQd 18 2K DQd 19 1L DQd 22 2M DQd 23 1N DQd ...
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... GW Document #: 38-05258 Rev. *A Boundary Scan Order (512K × 18) Bit# Bump CY7C1360A CY7C1362A (continued) Signal Name TQFP Bump ID CLK BWa 93 5L BWb 100 2A DQb 8 1D DQb 9 2E DQb 12 2G DQb DQb 18 2K DQb 19 1L DQb 22 2M DQb 23 1N DQb 24 2P MODE Page ...
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... Device deselected; all inputs < > all inputs static Max. CLK frequency = 0 CC Description Test Conditions T = 25° MHz 3.3V CC pins should be no greater than 200mV. CC < –2.0V for t < CY7C1360A CY7C1362A [18] [19] Ambient Temperature 3.3V 5/+10 – Min. Max. 2 0.3 CC 2.0 1.7 –0.3 0.8 – ...
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... CCQ 0 [15, 20, 26] 2.8 [28] 1.4 [28] 0.4 is less than t and t is less than t KQHZ KQLZ OEHZ , and CE are active CY7C1360A CY7C1362A TQFP Typ ALL INPUT PULSES V 90% CCQ 90% 10% GND 1 V/ns (c) 200 MHz 166 MHz 150 MHz Min. Max. Min. ...
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... ADSC ADSC t S ADDRESS BWE ADV ADV DQx SING LE READ Note: 30. For the X18 product, there are only BWa and BWb for byte Write control. Document #: 38-05258 Rev OELZ Q (A1) Q (A2) Q (A2+1) CY7C1360A CY7C1362A Q (A2+2) Q (A2+3) Q (A2) Q (A2+1) BURST READ Page ...
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... Write Timing CLK CLK t S ADSP ADSP ADSC ADSC t S ADDRESS BWE BW E Chan ADV ADV KQX DQ DQx Q SINGLE W RITE Document #: 38-05258 Rev OEHZ D(A1) D(A2) D(A2+1) D(A2+1) BURST W RITE CY7C1360A CY7C1362A D(A2+2) D(A2+3) D(A3) D(A3+1) BURST W RITE Page D(A3+2) ...
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... Switching Waveforms (continued) [29, 30] Read/Write Timing CLK CLK t S ADSP ADSP ADSC ADSC ADDRESS BWE ADV ADV DQx Single Reads Document #: 38-05258 Rev (A1) D(A3) Q (A2) Single W rite CY7C1360A CY7C1362A A5 Q (A4) Q (A4+1) Q (A4+2) D(A5) D(A5+1) Burst Read Burst W rite Page ...
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... LOW CE 2 HIGH I/Os Notes: 31. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device. 32. I/Os are in three-state when exiting ZZ sleep mode. Document #: 38-05258 Rev ZZS I (active DDZZ Three-state CY7C1360A CY7C1362A t ZZREC Page ...
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... Ordering Information Speed (MHz) Ordering Code 225 CY7C1360A-225AJC CY7C1360A-225AC CY7C1360A-225BGC 200 CY7C1360A-200AJC CY7C1360A-200AC CY7C1360A-200BGC 166 CY7C1360A-166AJC CY7C1360A-166AC CY7C1360A-166BGC 150 CY7C1360A-150AJC CY7C1360A-150AC CY7C1360A-150BGC 225 CY7C1362A-225AJC CY7C1362A-225AC CY7C1362A-225BGC 200 CY7C1362A-200AJC CY7C1362A-200AC CY7C1362A-200BGC 166 CY7C1362A-166AJC CY7C1362A-166AC CY7C1362A-166BGC 150 CY7C1362A-150AJC CY7C1362A-150AC CY7C1362A-150BGC 200 CY7C1360A-200AJI CY7C1360A-200AI ...
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... Package Diagrams 100-pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05258 Rev. *A CY7C1360A CY7C1362A 51-85050-A Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 119-Lead BGA ( 2.4) BG119 CY7C1360A CY7C1362A 51-85115-*A ...
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... Document Title:CY7C1360A CY7C1362A 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Document Number: 38-05258 Issue REV ECN No. Date ** 113846 05/22/02 *A 116062 05/28/02 Document #: 38-05258 Rev. *A Orig. of Change Description of Change GLC Change from Spec.: 38-00990 to 38-05258 BRI Removed GVT part numbers from title and body of datasheet Added note 19 (pg ...