CY7C1356B-200AC Cypress Semiconductor Corp, CY7C1356B-200AC Datasheet - Page 20

• Manufacturer Part Number: CY7C1356B-200AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1356B-200AC

• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05114 Rev. *C
Capacitance
AC Test Loads and Waveforms
Thermal Resistance
Switching Characteristics
C
C
C
t
Clock
t
F
t
t
Output Times
t
t
t
t
t
t
t
Shaded areas contain advance information.
Notes:
16. Tested initially and after any design or process changes that may affect these parameters.
17. This part has a voltage regulator internally; t
18. t
19. At any given voltage and temperature, t
20. This parameter is sampled and not 100% tested.
21. Timing reference level is 1.5V when V
22. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Power
CYC
CH
CL
CO
EOV
DOH
CHZ
CLZ
EOHZ
EOLZ
Parameters
MAX
Parameter
IN
CLK
I/O
OUTPUT
Parameter
initiated.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
CHZ
Θ
Θ
[17]
, t
JC
JA
CLZ
, t
EOLZ
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
[16]
, and t
Z
V
Write
Clock Cycle Time
Maximum Operating Frequency
Clock HIGH
Clock LOW
Data Output Valid after CLK Rise
OE LOW to Output Valid
Data Output Hold after CLK Rise
Clock to High-Z
Clock to Low-Z
OE HIGH to Output High-Z
OE LOW to Output Low-Z
0
CC
= 50Ω
EOHZ
Description
(typical) to the First Access Read or
(a)
Description
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
[16]
V
L
= 1.5V/1.25V
[18, 19, 20]
Description
[18, 19, 20]
R
DDQ
L
EOHZ
Over the Operating Range
= 50Ω
= 3.3V and is 1.25V when V
power
is less than t
Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, per EIA
/ JESD51.
is the time power needs to be supplied above V
[18, 19, 20]
[18, 19, 20]
T
V
INCLUDING
Test Conditions
V
A
DD
DQ
DDQ
EOLZ
JIG AND
= 25°C, f = 1 MHz,
SCOPE
= 3.3V V
Test Conditions
and t
5 pF
CHZ
DDQ
DDQ
is less than t
(b)
[21, 22]
= 2.5V.
Min.
1.25
1.25
1.25
= 2.5V
R=1667/317Ω
4.4
1.8
1.8
1
0
R = 1538/351Ω
-225
CLZ
BGA Typ.
Max.
to eliminate bus contention between SRAMs when sharing the same
225
2.8
2.8
2.8
2.8
25
BGA Max.
6
0V
V
DD
DD
5
5
7
< 1.0 ns
minimum initially, before a Read or Write operation can be
Min.
2.0
2.0
1.5
1.5
1.5
1
5
0
fBGA Typ.
10%
-200
90%
27
6
fBGA Max.
ALL INPUT PULSES
Max.
200
3.2
3.2
3.2
3.2
5
5
7
1.5/1.25V
TQFP Typ.
(c)
Min.
25
2.4
2.4
1.5
1.5
1.5
9
1
6
0
TQFP Max.
CY7C1356B
CY7C1354B
-166
5
[16]
5
5
Max.
166
3.5
3.5
3.5
3.5
°C/W
°C/W
90%
Unit
Page 20 of 29
10%
< 1.0 ns
Notes
MHz
Unit
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
pF
17
17