CY7C1347B-166AC Cypress Semiconductor Corp, CY7C1347B-166AC Datasheet - Page 10

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CY7C1347B-166AC

Manufacturer Part Number
CY7C1347B-166AC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1347B-166AC

Density
4Mb
Access Time (max)
3.5ns
Package Type
TQFP
Operating Temp Range
0C to 70C
Supply Current
420mA
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.63V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
36b
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C1347B-166AC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
AC Test Loads and Waveforms
Switching Characteristics
OUTPUT
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes:
10. Input waveform should have a slew rate of 1 V/ns.
11. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
12. t
13. At any given voltage and temperature, t
CYC
CH
CL
AS
AH
CO
DOH
ADS
ADH
WES
WEH
ADVS
ADVH
DS
DH
CES
CEH
CHZ
CLZ
OEHZ
OELZ
OEV
Parameter
loading of the specified I
voltage.
CHZ
, t
CLZ
, t
EOV
Z
0
Clock Cycle Time
Clock HIGH
Clock LOW
Address Set-Up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP , ADSC Set-Up Before CLK Rise
ADSP , ADSC Hold After CLK Rise
BWE, GW, BW
BWE, GW, BW
ADV Set-Up Before CLK Rise
ADV Hold After CLK Rise
Data Input Set-Up Before CLK Rise
Data Input Hold After CLK Rise
Chip Select Set-Up
Chip Select Hold After CLK Rise
Clock to High-Z
Clock to Low-Z
OE HIGH to Output High-Z
OE LOW to Output Low-Z
OE LOW to Output Valid
, t
=50
EOLZ
(a)
, and t
V
OL
L
EOHZ
/I
= 1.5V
OH
and load capacitance. Shown in (a) and (b) of AC test loads.
R
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state
[3:0]
[3:0]
[12]
L
[12]
Description
=50
Over the Operating Range
Set-Up Before CLK Rise
Hold After CLK Rise
EOHZ
is less than t
[12]
OUTPUT
[12, 13]
[12, 13]
INCLUDING
3.3V
JIG AND
SCOPE
EOLZ
5 pF
and t
CHZ
(b)
[11, 12, 13]
is less than t
R=317
10
Min.
6.0
1.7
1.7
1.5
0.5
1.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
0
0
R=351
-166
CLZ
Max.
.
3.5
3.5
3.5
3.5
GND
2.5V
2.5 ns
Min.
7.5
1.9
1.9
1.5
0.5
2.0
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
0
0
10%
-133
ALL INPUT PULSES
Max.
4.0
3.5
3.5
4.0
90%
(c)
Min.
CY7C1347B
3.5
3.5
1.5
0.5
2.0
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
10
0
0
-100
[10]
Max.
90%
5.5
3.5
5.5
5.5
10%
2.5 ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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