CY7C1340F-100AC Cypress Semiconductor Corp, CY7C1340F-100AC Datasheet
CY7C1340F-100AC
Specifications of CY7C1340F-100AC
Related parts for CY7C1340F-100AC
CY7C1340F-100AC Summary of contents
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... For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05219 Rev. *A Functional Description The CY7C1340F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK) ...
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... SLEEP ZZ CONTROL Document #: 38-05219 Rev A[1:0] Q1 BURST COUNTER AND LOGIC CLR BYTE WRITE DRIVER DQ C MEMORY BYTE ARRAY WRITE DRIVER DQ B BYTE WRITE DRIVER DQ A BYTE WRITE DRIVER PIPELINED ENABLE CY7C1340F OUTPUT OUTPUT SENSE DQs BUFFERS REGISTERS AMPS E INPUT REGISTERS Page ...
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... V 5 SSQ DQc 6 BYTE C DQc 7 DQc 8 DQc SSQ 11 V DDQ 12 DQc 13 DQc DDQ 21 V SSQ BYTE SSQ V 27 DDQ Document #: 38-05219 Rev. *A 100-pin TQFP Top View CY7C1340F 65 (128K x 32 CY7C1340F DDQ V SSQ DQ BYTE SSQ V DDQ DDQ V SSQ DQ BYTE SSQ V DDQ Page ...
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... The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs are placed in a three-state condition. Ground for the core of the device. Power supply for the I/O circuitry. CY7C1340F , CE , and ...
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... Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1340F is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the safety precaution, DQ whenever a write cycle is detected, regardless of the state of OE ...
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... Burst Sequences The CY7C1340F provides a two-bit wraparound counter, fed that implements either an interleaved or linear burst [1:0] sequence. The interleaved burst sequence is designed specif- ically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input ...
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... [ BWE and BWE = WRITE = H when all Byte write enable signals valid. Appropriate write will be done based on which byte write is [A:D] CY7C1340F ADV WRITE OE CLK L-H Three-State L-H Three-State L-H Three-State L-H Three-State L-H Three-State Three-State L L-H Three-State L L L-H Three-State L-H ...
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... MAX 1/t CYC /2), undershoot: V (AC)> –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < CY7C1340F Ambient Temperature ( 3.3V −5%/+10% 2.5V −5% 0°C to +70°C –40°C to +85°C Min. Max. 3.135 3.6 2.375 V 2.4 2.0 0.4 0.4 2 ...
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... All speeds DD ≥ V ≤ Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. Description Test Conditions T = 25° MHz 3. 3.3V DDQ CY7C1340F Min. Max. Unit 40 mA 105 mA 100 TQFP Package Unit 41.83 °C/W 9.99 ° ...
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... Document #: 38-05219 Rev 317Ω 3.3V OUTPUT 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V OUTPUT =1538Ω INCLUDING JIG AND (b) SCOPE CY7C1340F ALL INPUT PULSES V DD 90% 10% GND ≤ 1ns (c) ALL INPUT PULSES V DD 90% 10% GND ≤ 1ns (c) Page 90% 10% ≤ ...
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... POWER is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ = 3.3V and is 1.25V when V = 2.5V. DDQ CY7C1340F 200 MHz 166 MHz 133 MHz 1.0 1.0 1.0 5.0 6.0 7.5 2.0 2.5 3 ...
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... ADV suspends burst t OEV OELZ t OEHZ t DOH Q(A2) Q( Q(A1) DON’T CARE is HIGH and CE is LOW. When CE is HIGH CY7C1340F A3 Burst continued with new base address Deselect cycle Q( Q( Q(A2) Q( Burst wraps around to its initial state BURST READ UNDEFINED is HIGH LOW HIGH ...
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... Full width write can be initiated by either GW LOW HIGH, BWE LOW and BW Document #: 38-05219 Rev WES t WEH t DH D(A2 BURST WRITE DON’T CARE [A:D] CY7C1340F ADSC extends burst t ADS t ADH A3 t WES t WEH t ADVS t ADVH ADV suspends burst D( D( D(A3) ...
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... The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 20 HIGH. Document #: 38-05219 Rev WES t WEH OELZ D(A3) t OEHZ Q(A2) Single WRITE DON’T CARE CY7C1340F A5 D(A5) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) BURST READ UNDEFINED A6 D(A6) Back-to-Back WRITEs Page ...
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... CY7C1340F-225AC CY7C1340F-225AI 200 CY7C1340F-200AC CY7C1340F-200AI 166 CY7C1340F-166AC CY7C1340F-166AI 133 CY7C1340F-133AC CY7C1340F-133AI 100 CY7C1340F-100AC CY7C1340F-100AI Shaded area contains advance information. Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05219 Rev ZZI I DDZZ High-Z DON’T CARE Package Name A101 100-Lead ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1340F 51-85050-*A ...
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... Document History Page Document Title: CY7C1340F 4-Mb (128K x 32) Pipelined DCD Sync SRAM Document Number: 38-05219 REV. ECN NO. Issue Date ** 119827 12/16/02 *A 200143 See ECN Document #: 38-05219 Rev. *A Orig. of Change HGK New Data Sheet SWI Final Data Sheet CY7C1340F Description of Change ...