CY7C1338F-117AC Cypress Semiconductor Corp, CY7C1338F-117AC Datasheet
CY7C1338F-117AC
Specifications of CY7C1338F-117AC
Related parts for CY7C1338F-117AC
CY7C1338F-117AC Summary of contents
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... Offered in JEDEC-standard 100-pin TQFP and 119-ball BGA packages • “ZZ” Sleep Mode option [1] Functional Description The CY7C1338F is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is Logic Block Diagram A0, A1, A ...
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... V 11 DDQ DDQ V 21 SSQ BYTE SSQ V 27 DDQ Document #: 38-05218 Rev. *A 133 MHz 117 MHz 6.5 7.5 225 220 40 40 100-Pin TQFP CY7C1338F CY7C1338F 100 MHz 66 MHz 8.0 11.0 205 195 DDQ 76 V SSQ BYTE SSQ 70 V DDQ DDQ 60 V SSQ ...
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... Output Enable, asynchronous input, active LOW. Controls the direction Asynchronous of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins masked during the first clock of a read cycle when emerging from a deselected state. CY7C1338F ...
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... When tied left floating selects interleaved burst sequence. This strap pin and should remain static during device operation. Mode Pin has an internal pull-up. No Connects. Not Internally connected to the die. CY7C1338F Description are also loaded into the burst [1:0] is deasserted HIGH 1 are also loaded into the burst counter. ...
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... Maximum access delay from the clock rise ( 6.5 ns (133-MHz device). C0 The CY7C1338F supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium processors. The linear burst sequence is suited for processors that utilize a linear burst sequence ...
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... and BWE = L or GW= L. WRITE = H when all Byte write enable signals CY7C1338F Min. Max. Unit CYC 2t ns CYC 2t ns CYC CLK L-H three-state L-H three-state L-H three-state L-H three-state L-H three-state three-state L L-H three-state L L L-H three-state L L-H three-state L L-H three-state ...
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... Write Bytes B, A Write Byte C Write Bytes C, A Write Bytes C, B Write Bytes Write Byte D Write Bytes D, A Write Bytes D, B Write Bytes Write Bytes D, B Write Bytes Write Bytes Write All Bytes Write All Bytes Document #: 38-05218 Rev BWE CY7C1338F ...
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... V – 0. inputs static /2), undershoot: V (AC) > -2V (Pulse width less than t CYC IL (min.) within 200ms. During this time V < CY7C1338F Ambient ] Temperature V DD 3.3V −5%/+10% 2.5V –5% 0°C to +70°C –40°C to +85°C CY7C1345F Min. 3.135 2.375 = –4.0 mA 2.4 = – ...
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... R = 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V OUTPUT =1538Ω INCLUDING JIG AND (b) SCOPE CY7C1338F CY7C1345F Min. Max. 7.5-ns cycle, 133 MHz 8.0-ns cycle, 117 MHz 10-ns cycle, 100 MHz 15-ns cycle, 66 MHz All speeds TQFP BGA Package Package 41 ...
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... V POWER is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ = 3.3V and is 1.25V when V = 2.5V. DDQ CY7C1338F 117 MHz 100 MHz 66 MHz Max 8 3.0 4 ...
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... A2 t WEH t t ADVH ADVS t CDV t OELZ t OEHZ t DOH Q(A2) Q( DON’T CARE is HIGH and CE is LOW. When CE is HIGH CY7C1338F ADV suspends burst Q(A2) Q( Burst wraps around to its initial state BURST READ UNDEFINED is HIGH LOW HIGH Deselect Cycle t CHZ ...
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... Full width write can be initiated by either GW LOW HIGH, BWE LOW and BW Document #: 38-05218 Rev WES WEH DH D(A2 BURST WRITE DON’T CARE UNDEFINED [A:D] CY7C1338F ADSC extends burst t ADS t ADH A3 t WES t WEH t ADVS t ADVH ADV suspends burst D( D( D(A3) D( Extended BURST WRITE LOW ...
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... The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC . 20 HIGH. Document #: 38-05218 Rev WEH WES OELZ D(A3) t OEHZ t CDV Q(A4) Single WRITE DON’T CARE CY7C1338F A5 D(A5) Q(A4+1) Q(A4+2) Q(A4+3) BURST READ Back-to-Back WRITEs UNDEFINED A6 D(A6) Page ...
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... SUPPLY ALL INPUTS (except ZZ) Outputs (Q) Ordering Information Speed (MHz) Ordering Code 133 CY7C1338F-133AC CY7C1338F-133BGC CY7C1338F-133AI CY7C1338F-133BGI 117 CY7C1338F-117AC CY7C1338F-117BGC CY7C1338F-117AI CY7C1338F-117BGI 100 CY7C1338F-100AC CY7C1338F-100BGC CY7C1338F-100AI CY7C1338F-100BGI 66 CY7C1338F-66AC CY7C1338F-66BGC CY7C1338F-66AI CY7C1338F-66BGI Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. ...
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... MIN. 1.00 REF. DETAIL Document #: 38-05218 Rev. *A DIMENSIONS ARE IN MILLIMETERS. 16.00±0.20 14.00±0. 0.30±0.08 0.65 TYP STAND-OFF 0.05 MIN. SEATING PLANE 0.15 MAX. A CY7C1338F 1.40±0.05 12°±1° A SEE DETAIL (8X) 0.20 MAX. 1.60 MAX. 51-85050-*A Page ...
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... Package Diagrams (continued) Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05218 Rev. *A 119-Lead PBGA ( 2.4 mm) BG119 CY7C1338F 51-85115-*B Page ...
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... Document History Page Document Title: CY7C1338B 4-Mb (128K x 32) Flow-Through Sync SRAM Document Number: 38-05218 REV. ECN NO. Issue Date ** 119832 12/11/02 *A 200663 12/19/03 Document #: 38-05218 Rev. *A Orig. of Change HGK New Data Sheet SWI Final Data Sheet CY7C1338F Description of Change Page ...