CY7C1049CV33-20VI Cypress Semiconductor Corp, CY7C1049CV33-20VI Datasheet - Page 7

• Manufacturer Part Number: CY7C1049CV33-20VI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1049CV33-20VI

• Density: 4Mb
• Access Time (max): 20ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: SOJ
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 90mA
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 36
• Word Size: 8b
• Number Of Words: 512K
• Lead Free Status / Rohs Status: Not Compliant

AC Switching Characteristics
Over the Operating Range
Notes
Document #: 38-05006 Rev. *H
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. t
7. t
8. At any given temperature and voltage condition, t
9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of
10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
power
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
Parameter
these signals can terminate the Write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the Write.
POWER
HZOE
[6]
, t
HZCE
gives the minimum amount of time that the power supply should be at stable, typical V
, and t
[9, 10]
V
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
CE LOW to Low-Z
CE HIGH to High-Z
CE LOW to Power Up
CE HIGH to Power Down
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low-Z
WE LOW to High-Z
CC
HZWE
(typical) to the first access
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
[5]
Description
[8]
[7, 8]
[8]
[7, 8]
[7, 8]
HZCE
is less than t
LZCE
, t
HZOE
Min
100
10
10
3
0
3
0
7
7
0
0
7
5
0
3
is less than t
-10
Max
10
10
10
5
5
5
5
LZOE
, and t
HZWE
CC
values until the first memory access can be performed.
HZWE
Min
100
12
12
and t
3
0
3
0
8
8
0
0
8
6
0
3
is less than t
SD
-12
.
Max
12
12
12
6
6
6
6
LZWE
for any given device.
Min
100
15
15
10
10
10
0
3
0
0
0
7
0
3
CY7C1049CV33
-15
Max
15
15
15
3
7
7
7
7
Page 7 of 12
Unit
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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