CY7C1046CV33-10VC Cypress Semiconductor Corp, CY7C1046CV33-10VC Datasheet

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CY7C1046CV33-10VC

Manufacturer Part Number
CY7C1046CV33-10VC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1046CV33-10VC

Density
4Mb
Access Time (max)
10ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3.3V
Address Bus
20b
Package Type
SOJ
Operating Temp Range
0C to 70C
Number Of Ports
1
Supply Current
90mA
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Word Size
4b
Number Of Words
1M
Lead Free Status / Rohs Status
Not Compliant
Cypress Semiconductor Corporation
Document #: 38-05003 Rev. *A
Features
Functional Description
The CY7C1046CV33 is a high-performance CMOS static
RAM organized as 1,048,576 words by 4 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers.
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Notes:
• High speed
• Low active power for 10 ns speed
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
1.
2.
CE
WE
OE
Logic Block Diagram
— t
— 324 mW (max.)
A
For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Shaded areas contain advance information.
A
A
A
A
A
A
A
A
A
A
10
0
1
2
3
4
5
6
7
8
9
AA
= 10ns
INPUT BUFFER
DECODER
COLUMN
1M x 4
ARRAY
[1]
POWER
DOWN
-8
100
10
3901 North First Street
8
[2]
I/O
I/O
I/O
I/O
-10
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the four I/O
pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The four input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
The CY7C1046CV33 is available in a standard 400-mil-wide
32-pin SOJ package with center power and ground (revolu-
tionary) pinout.
10
90
10
0
1
2
3
0
San Jose
through I/O
GND
V
I/O
I/O
WE
CE
A
A
A
A
A
A
A
A
A
A
CC
5
6
7
8
9
0
1
2
3
4
0
1
Pin Configuration
-12
12
85
10
11
12
13
14
15
16
1M x 4 Static RAM
1
2
3
4
5
6
7
8
9
10
3
Top View
) is then written into the location
SOJ
CA 95134
0
Revised September 13, 2002
22
21
20
19
18
17
through I/O
0
32
31
30
29
28
27
26
25
24
23
through A
CY7C1046CV33
A
A
A
A
A
A
NC
A
A
A
A
OE
I/O
GND
V
I/O
-15
19
14
13
12
11
10
18
17
16
15
CC
15
80
10
3
2
19
3
) are placed in a
).
408-943-2600
Unit
mA
mA
ns
[+] Feedback

Related parts for CY7C1046CV33-10VC

CY7C1046CV33-10VC Summary of contents

Page 1

... I/O pins. The four input/output pins (I/O high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a Write operation (CE LOW, and WE LOW). The CY7C1046CV33 is available in a standard 400-mil-wide 32-pin SOJ package with center power and ground (revolu- tionary) pinout ...

Page 2

... MAX > > < MAX , Commercial 10 CC – 0.3V, CC > V – 0.3V, CC < 0.3V, IN Test Conditions MHz 3. CY7C1046CV33 Ambient Temperature +70 C 3.0V – 3.6V – 3.0V – 3.6V -10 -12 -15 Unit 2.4 2.4 2.4 V 0.4 0.4 0.4 V 2.0 V 2 0.3 + 0.3 + 0.3 – ...

Page 3

... Thevenin load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d). Document #: 38-05003 Rev. *A [5] 12-, 15-ns devices: OUTPUT 50 30 pF* 1.5V (a) High-Z characteristics: 90% OUTPUT 10% (c) Fall Time: 1 V/ns CY7C1046CV33 R 317 3. 351 (b) R 317 3. 351 (d) Page [+] Feedback ...

Page 4

... The minimum Write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t Document #: 38-05003 Rev. *A Over the Operating Range [2] -8 -10 Min. Max. Min less than less than t , and t HZCE LZCE HZOE LZOE and t HZWE CY7C1046CV33 -12 -15 Max. Min. Max. Min. Max. Unit ...

Page 5

... No input may exceed V + 0.5V. CC 14. Device is continuously selected HIGH for Read cycle. 16. Address valid prior to or coincident with CE transition LOW. Document #: 38-05003 Rev OHA DOE DATA VALID 50% CY7C1046CV33 DATA VALID t HZOE t HZCE HIGH IMPEDANCE 50 Page [+] Feedback ...

Page 6

... If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 19. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05003 Rev SCE SA t SCE PWE t SD DATA VALID [17, 18 SCE PWE t SD DATA VALID IN CY7C1046CV33 Page [+] Feedback ...

Page 7

... NOTE DATA I/O t HZWE Truth Table High Data Out Data High-Z Ordering Information Speed (ns) Ordering Code 10 CY7C1046CV33-10VC CY7C1046CV33-10VI 12 CY7C1046CV33-12VC CY7C1046CV33-12VI 15 CY7C1046CV33-15VC CY7C1046CV33-15VI Document #: 38-05003 Rev. *A [18 SCE PWE t SD DATA VALID I/O – I/O Mode 0 7 Power-down Read Write Selected, Outputs Disabled ...

Page 8

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 32-Lead (400-Mil) Molded SOJ V33 CY7C1046CV33 51-85033-*B Page ...

Page 9

... Document History Page Document Title: CY7C1046CV33 Static RAM Document Number: 38-05003 Issue REV. ECN NO. Date ** 112570 03/06/02 *A 116478 09/16/02 Document #: 38-05003 Rev. *A Orig. of Change Description of Change HGK New data sheet for RAM 7 CEA Add applications foot note to data sheet, page 1. CY7C1046CV33 ...

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