CY7C1041CV33-10ZXC Cypress Semiconductor Corp, CY7C1041CV33-10ZXC Datasheet - Page 6

• Manufacturer Part Number: CY7C1041CV33-10ZXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1041CV33-10ZXC

• Density: 4Mb
• Access Time (max): 10ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 90mA
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Word Size: 16b
• Number Of Words: 256K
• Lead Free Status / Rohs Status: Compliant

Switching Characteristics
Over the Operating Range
Notes
Document Number: 38-05134 Rev. *J
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V.
5. t
6. At any temperature and voltage condition, t
7. t
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write.
9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
power
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
BW
Parameter
mV from steady state voltage.
The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write.
POWER
HZOE
[5]
, t
HZCE
gives the minimum amount of time that the power supply is at typical V
[8, 9]
, t
HZBE
V
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power Up
CE HIGH to Power Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
Byte Enable to End of Write
CC
, and t
(Typical) to the First Access
HZWE
[4]
are specified with a load capacitance of 5 pF as in part (d) of
Description
[6]
[6]
[6, 7]
[6]
[6, 7]
[6, 7]
HZCE
is less than t
Comm’l/Ind’l/Auto-A
Comm’l/Ind’l/Auto-A
Auto-E
Auto-E
LZCE
, t
HZBE
is less than t
CC
Min
100
values until the first memory access is performed.
10
10
3
0
3
0
0
7
7
0
0
7
5
0
3
7
LZBE
-10
Max
, t
10
10
10
5
5
5
5
6
5
HZOE
AC Test Loads and Waveforms
HZWE
is less than t
and t
Min
100
12
12
3
0
3
0
0
8
8
0
0
8
6
0
3
8
SD
-12
.
Max
12
12
12
6
7
6
6
6
7
6
6
LZOE
, and t
Min
100
15
15
10
10
10
10
3
0
3
0
0
0
0
7
0
3
HZWE
-15
on page 5. Transition is measured 500
Max
15
15
15
7
7
7
7
7
7
is less than t
CY7C1041CV33
Min
100
20
20
10
10
10
10
3
0
3
0
0
0
0
8
0
3
-20
LZWE
Max
20
20
20
8
8
8
8
8
8
8
8
for any device.
Page 6 of 14
Unit
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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