CY7C1031-10JC Cypress Semiconductor Corp, CY7C1031-10JC Datasheet

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CY7C1031-10JC

Manufacturer Part Number
CY7C1031-10JC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1031-10JC

Density
1Mb
Access Time (max)
10ns
Operating Supply Voltage (typ)
5V
Package Type
LCC
Operating Temp Range
0C to 70C
Supply Current
280mA
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
52
Word Size
18b
Lead Free Status / Rohs Status
Not Compliant
Cypress Semiconductor Corporation
Document #: 38-05278 Rev. *A
Features
Selection Guide
Maximum Access Time
Maximum Operating Current
Note:
• Supports 66-MHz Pentium
• 64K by 18 common I/O
• Fast clock-to-output times
• Two-bit wraparound counter supporting Pentium
• Two-bit wraparound counter supporting linear burst
• Separate processor and controller address strobes
• Synchronous self-timed write
• Direct interface with the processor and external cache
• Asynchronous output enable
• I/Os capable of 3.3V operation
• JEDEC-standard pinout
• 52-pin PLCC packaging
1. DP
Logic Block Diagram
A
systems with zero wait states
— 8.5 ns
microprocessor and 486 burst sequence (CY7C1031)
sequence (CY7C1032)
controller
15
ADV
ADSP
ADSC
–A
0
WH
CLK
CS
WL
0
OE
and DP
1
are functionally equivalent to DQ
16
2
14
LOGIC
ADDR
CONTROL
REG
ADV
TIMING
14
2
®
microprocessor cache
WH
16
WL
x
.
Commercial
RAM ARRAY
64K X 9
3901 North First Street
9
9
REGISTER
DATA
RAM ARRAY
18
18
IN
64K X 9
64K x 18 Synchronous Cache RAM
9
9
Functional Description
The CY7C1031 and CY7C1032 are 64K by 18 synchronous
cache RAMs designed to interface with high-speed micropro-
cessors with minimum glue logic. Maximum access delay from
clock rise is 8.5 ns. A 2-bit on-chip counter captures the first
address in a burst and increments the address automatically
for the rest of the burst access.
The CY7C1031 is designed for Intel
CPU-based systems; its counter follows the burst sequence of
the Pentium and the i486 processors. The CY7C1032 is archi-
tected for processors with linear burst sequences. Burst
accesses can be initiated with the processor address strobe
(ADSP) or the cache controller address strobe (ADSC) inputs.
Address advancement
advancement (ADV) input.
A synchronous self-timed write mechanism is provided to
simplify the write interface. A synchronous chip select input
and an asynchronous output enable input provide easy control
for bank selection and output three-state control.
7C1031-8
7C1032-8
280
8.5
DP
V
DQ
DQ
DQ
DQ
V
DQ
DQ
V
V
San Jose
DQ
DQ
CCQ
CCQ
SSQ
SSQ
1
[1]
10
11
12
13
14
15
8
9
DQ
DP
8
9
10
11
12
13
14
15
16
17
18
19
20
7C1031-10
7C1032-10
1
15
– DP
2122 23 24 25 26 27 28 29 30 31 32 33
– DQ
7 6 5 4 3 2
280
Pin Configuration
,
10
0
CA 95134
is controlled by the
0
Top View
7C1031
7C1032
PLCC
1
52 51 50 49 48 47
®
7C1031-12
Revised April 1, 2004
Pentium and i486
230
12
CY7C1031
CY7C1032
408-943-2600
46
45
44
43
42
41
40
39
38
37
36
35
34
address
DP
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
Unit
mA
CCQ
SSQ
SSQ
CCQ
ns
0
7
6
5
4
3
2
1
0
[1]

Related parts for CY7C1031-10JC

CY7C1031-10JC Summary of contents

Page 1

... Document #: 38-05278 Rev. *A 64K x 18 Synchronous Cache RAM Functional Description The CY7C1031 and CY7C1032 are 64K by 18 synchronous cache RAMs designed to interface with high-speed micropro- cessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access ...

Page 2

... If the write is allowed to proceed, the write input to the CY7C1031 and CY7C1032 will be pulled LOW before the next clock rise. ADSP is ignored HIGH. If WH, WL, or both are LOW at the next clock rise, information presented at DQ – ...

Page 3

... Application Example Figure 1 shows a 512-Kbyte secondary cache for the Pentium microprocessor using four CY7C1031 cache RAMs. 66-MHz OSC CLK ADR DATA ADS PENTIUM PROCESSOR CLK ADR CD CACHE DATA TAG MATCH DIRTY VALID Pin Definitions Signal Name Type V Input CC V Input CCQ ...

Page 4

... Advance. This signal is sampled by the rising edge of CLK. When it is asserted, it automatically increments the 2-bit on-chip auto-address-increment counter. In the CY7C1032, the address will be incremented linearly. In the CY7C1031, the address will be incremented according to the Pentium/486 burst sequence. This signal is ignored if ADSP or ADSC is asserted concurrently with CS ...

Page 5

... MAX , CS ≥ Max. V Com’l CC ≥ V – 0.3V ≤ V – 0. [6] 0.3V Test Conditions ° MHz 5.0V CC CY7C1031 CY7C1032 [2] ...........................................–0. Ambient [3] Temperature V CC ° ° 5V ± + 7C1031-10 7C1031-12 7C1032-10 Min. Max. Min. Max. 2.4 V 2.4 V CCQ CCQ CCQ 0.4 ...

Page 6

... INCLUDING JIGAND [8] SCOPE (b) [9] Description Min. 15 [11] [11] [11, 12] [12] = 3.3V are R1 = 317Ω and R2 = 348Ω. CCQ min. is less than t min. WEOV CY7C1031 CY7C1032 ALL INPUT PULSES 3.0V 90% 10% GND ≤ 7C1031-8 7C1031-10 7C1031-12 7C1032-8 7C1032-10 Max. Min. Max. Min. [10] ...

Page 7

... OE is LOW throughout this operation. 14. If ADSP is asserted while CS is HIGH, ADSP will be ignored. 15. ADSP has no effect on ADV, WL, and HIGH. Document #: 38-05278 Rev CSS CSH ADS ADSH t t WES WEH t CDV CSH ADSH t WES EOZ CY7C1031 CY7C1032 t CYC t DOH t WEH t DH Page ...

Page 8

... Burst Read Sequence with Four Accesses CLK t t CSS CSH ADDRESS t t ADS ADSH [14] ADSP or ADSC [15] ADV t [15] WES WH, CDV DATA OUT OE Document #: 38-05278 Rev CSS CSH ADS ADSH t t WES WEH ADVS ADVH t WEH t DOH DATA0 DATA1 CY7C1031 CY7C1032 t CL DATA2 DATA3 Page ...

Page 9

... Output (Controlled by OE) DATA OUT OE Write Burst Timing: Write Initiated by ADSC CLK t t CSS CSH WES WEH WH ADS ADSH [14] ADSP t t ADS ADSH ADSC ADDR ADV DATA DATA0 Document #: 38-05278 Rev EOZ EOV t t ADVS ADVH DATA1 DATA2 CY7C1031 CY7C1032 DATA3 Page ...

Page 10

... CSS CSH CS [15] WH ADSC t t ADS ADSH [14] ADSP ADDR [15] ADV DATA Output Timing (Controlled by CS) CLK t ADS ADSC t CSS CS DATA OUT Document #: 38-05278 Rev ADVS ADVH DATA1 DATA0 t ADS t ADSH t CSS t CSH t CDV CY7C1031 CY7C1032 DATA2 DATA3 t ADSH t CSH t CSOZ Page ...

Page 11

... Ordering Information Speed (ns) Ordering Code 8 CY7C1031-8JC 10 CY7C1031-10JC 12 CY7C1031-12JC 8 CY7C1032-8JC [16] 10 CY7C1032-10JC Note: 16. EOL (End of Life). Document #: 38-05278 Rev ADSH t ADS t WEH t WEOZ CLK Address X L→H N/A H L→H Same address as previous cycle Read cycle (ADSP ignored) H L→H Incremented burst address L L→ ...

Page 12

... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 52-Lead Plastic Leaded Chip Carrier J69 SEATING PLANE 0.045 0.055 34 0.023 0.033 33 0.750 0.756 CY7C1031 CY7C1032 MIN. DIMENSIONS IN INCHES MAX. 0.013 0.021 0.690 0.730 0.020 MIN. 0.090 0.130 0.165 51-85004-*A ...

Page 13

... Document History Page Document Title: CY7C1031/CY7C1032 64K x 18 Synchronous Cache RAM Document Number: 38-05278 REV. ECN NO. Issue Date ** 114203 3/19/02 *A 212291 See ECN Document #: 38-05278 Rev. *A Orig. of Change DSG Change from Spec number: 38-00219 to 38-05278 VBL Update ordering info by deleting CY7C1032-12 by adding EOL note to ...

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