CY7C1024AV33-12BGI Cypress Semiconductor Corp, CY7C1024AV33-12BGI Datasheet
CY7C1024AV33-12BGI
Specifications of CY7C1024AV33-12BGI
Related parts for CY7C1024AV33-12BGI
CY7C1024AV33-12BGI Summary of contents
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... The 24 input/output pins (I/O high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE1, CE3 LOW, CE2 HIGH, and WE LOW). The CY7C1024AV33 is available in a standard 119-ball BGA package and a 100-pin TQFP package. MEMORY ARRAY 128K X 24 ...
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... Pin Configurations Document #: 38-05149 Rev. *B 119 BGA Top View CE1 A NC CE2 NC CE3 CY7C1024AV33 Page ...
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... Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA Operating Range [2] .... –0.5V to +7.0V Range Commercial + 0.5V CC Industrial + 0.5V CC CY7C1024AV33 NC 80 VCC 79 VSS 78 77 DQ0 76 DQ1 VSS 75 VCC 74 DQ2 73 DQ3 72 VSS 71 70 VCC 69 DQ4 DQ5 ...
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... CC V > V – 0.3V < 0.3V Test Conditions MHz 3. 480 3.3V R2 GND 5 pF 255 INCLUDING JIG AND SCOPE (b) 1.73V CY7C1024AV33 1024AV33-12 1024AV33-15 Min. Max. Min. 2.4 2.4 0.4 2 0.3 –0.3 0.8 –0.3 –3 +3 –3 –5 +5 –5 250 60 15 Max. ...
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... The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t Document #: 38-05149 Rev. *B 7C1024AV33-10 7C1024AV33-12 Min. Max. Min less than less than t , and t HZCE LZCE HZOE LZOE HZWE CY7C1024AV33 7C1024AV33-15 Max. Min. Max less than t for any given device. HZWE LZWE and Page Unit ...
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... Address valid prior to or coincident with CE transition LOW. 13. Data I/O is high impedance 14 goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05149 Rev OHA t RC ACE t DOE LZOE 50 SCE PWE t DATA VALID . IL CY7C1024AV33 DATA VALID t HZOE t HZCE DATA VALID t PD 50% SCE HIGH IMPEDANCE Page ...
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... Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS NOTE 15 DATA I/O t Note: 15. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05149 Rev. *B [13, 14 SCE PWE t SD DATA [3, 14 SCE PWE HZWE CY7C1024AV33 VALID DATA VALID t LZWE Page ...
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... Ordering Information Speed (ns) Ordering Code 10 CY7C1024AV33-10AC CY7C1024AV33-10BGC 12 CY7C1024AV33-12AC CY7C1024AV33-12BGC CY7C1024AV33-12BGI 15 CY7C1024AV33-15AC CY7C1024AV33-15BGC CY7C1024AV33-15BGI Document #: 38-05149 Rev I/O –I High Z Power-Down X High Z Power-Down X High Z Power-Down H Data Out Read L Data In Write H High Z Selected, Outputs Disabled Package Name Package Type A101 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) ...
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... Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05149 Rev. *B CY7C1024AV33 51-85050-*A Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 119-Lead PBGA ( 2.4 mm) BG119 CY7C1024AV33 51-85115-*B Page ...
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... Document History Page Document Title: CY7C1024AV33 128K x 24 Static RAM Document Number: 38-05149 Issue REV. ECN NO. Date ** 109893 09/22/01 *A 116473 09/16/02 *B 121472 11/14/02 Document #: 38-05149 Rev. *B Orig. of Change Description of Change SZV Change from Spec number: 38-00983 to 38-05149 CEA Add applications foot note to data sheet, page 1. ...