CY62147DV18LL-70BVI Cypress Semiconductor Corp, CY62147DV18LL-70BVI Datasheet

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CY62147DV18LL-70BVI

Manufacturer Part Number
CY62147DV18LL-70BVI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY62147DV18LL-70BVI

Density
4Mb
Access Time (max)
70ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
1.8V
Address Bus
18b
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Number Of Ports
1
Supply Current
10mA
Operating Supply Voltage (min)
1.65V
Operating Supply Voltage (max)
2.25V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Word Size
16b
Number Of Words
256K
Lead Free Status / Rohs Status
Not Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
CY62147DV18LL-70BVIT
Quantity:
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Cypress Semiconductor Corporation
Document #: 38-05343 Rev. *B
Features
Functional Description
The CY62147DV18 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL™) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption. The device can also be put into standby
Note:
1.
• Very high speed: 55 ns and 70 ns
• Wide voltage range: 1.65V – 2.25V
• Pin-compatible with CY62147CV18
• Ultra-low active power
• Ultra low standby power
• Easy memory expansion with CE, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered 48-ball BGA
— Typical active current: 1 mA @ f = 1 MHz
— Typical active current: 6 mA @ f = f
For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
Pow er
Circuit
[1]
A
A
A
A
A
A
A
A
A
A
A
10
6
5
4
3
2
1
0
9
8
7
-
Down
max
COLUMN DECODER
3901 North First Street
DATA IN DRIVERS
RAM Array
256K x 16
mode reducing power consumption by more than 99% when
deselected (CE HIGH or both BLE and BHE are HIGH). The
input/output pins (I/O
pedance state when: deselected (CE HIGH), outputs are dis-
abled (OE HIGH), both Byte High Enable and Byte Low Enable
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW and WE LOW).
Writing to the device is accomplished by asserting Chip En-
able (CE) and Write Enable (WE) inputs LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O
I/O
(A
from I/O pins (I/O
specified on the address pins (A
Reading from the device is accomplished by asserting Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
LOW, then data from memory will appear on I/O
the truth table for a complete description of read and write
modes.
The CY62147DV18 is available in a 48-ball FBGA package.
0
7
4-Mb (256K x 16) Static RAM
through A
), is written into the location specified on the address pins
17
San Jose
). If Byte High Enable (BHE) is LOW, then data
8
through I/O
0
through I/O
0
to I/O
,
I/O
I/O
CA 95134
0
8
– I/O
– I/O
7
BHE
WE
CE
OE
BLE
. If Byte High Enable (BHE) is
15
0
7
15
) is written into the location
Revised February 26, 2004
through A
15
) are placed in a high-im-
CY62147DV18
17
).
408-943-2600
MoBL2™
8
to I/O
0
through
15
. See
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CY62147DV18LL-70BVI Summary of contents

Page 1

... Circuit Note: 1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05343 Rev. *B 4-Mb (256K x 16) Static RAM mode reducing power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The ...

Page 2

Pin Configuration Notes pins are not internally connected on the die. 3. DNU pins have to be left floating or tied to Vss to ensure proper application. 4. Pins H1, G2, and H6 in the ...

Page 3

... Document #: 38-05343 Rev. *B Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Operating Range Device + 0.2V CC(MAX) CY62147DV18L Industrial –40°C to +85°C 1.65V to 2.25V + 0.2V CY62147DV18LL CC(MAX) + 0.2V CC (MAX) Operating 1MHz Speed [7] Max. (ns) Typ. ...

Page 4

Electrical Characteristics Over the Operating Range Parameter Description −0.2V, I Automatic CE CE > V SB1 CC Power-Down V >V –0.2V Current — V <0.2V CMOS Inputs (Address and Data Only ...

Page 5

Data Retention Waveform wqewqewq BHE.BLE Switching Characteristics Over the Operating Range Parameter Description Read Cycle t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t CE ...

Page 6

Switching Waveforms Read Cycle 1 (Address Transition Controlled) ADDRESS DATA OUT PREVIOUS DATA VALID [15, 16] Read Cycle No. 2 (OE Controlled) ADDRESS CE t ACE OE BHE/BLE t LZOE t DBE t LZBE HIGH IMPEDANCE DATA OUT t LZCE ...

Page 7

Switching Waveforms (continued) [13, 17, 18] Write Cycle No. 1 (WE Controlled) ADDRESS BHE/BLE OE 19 DATA I/O NOTE t HZOE [13, 17, 18] Write Cycle No. 2 (CE Controlled) ADDRESS CE WE BHE/BLE OE DATA ...

Page 8

Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS CE BHE/BLE NOTE 19 DATAI/O t Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) ADDRESS CE BHE/BLE DATA I/O NOTE 19 Document ...

Page 9

... Ordering Information Speed (ns) Ordering Code 55 CY62147DV18L-55BVI CY62147DV18LL-55BVI 70 CY62147DV18L-70BVI CY62147DV18LL-70BVI 55 CY62147DV18L-55BVXI CY62147DV18LL-55BVXI 70 CY62147DV18L-70BVXI CY62147DV18LL-70BVXI Document #: 38-05343 Rev. *B Inputs/Outputs X High Z Deselect/Power-Down High Z Deselect/Power-Down L Data Out (I/O –I/O ) Read Data Out (I/O –I/O ); Read (Lower byte only I/O –I/O in High Data Out (I/O –I/O ) ...

Page 10

... Document #: 38-05343 Rev. *B © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

Page 11

Document History Page Document Title:CY62147DV18 MoBL2™ 4-Mb (256K x 16) Static RAM Document Number: 38-05343 Issue Orig. of REV. ECN NO. Date Change ** 127482 06/17/03 *A 131009 11/26/03 *B 229908 See ECN Document #: 38-05343 Rev. *B Description of ...

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