CY62136VLL-55ZI Cypress Semiconductor Corp, CY62136VLL-55ZI Datasheet

CY62136VLL-55ZI

Manufacturer Part Number
CY62136VLL-55ZI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY62136VLL-55ZI

Density
2Mb
Access Time (max)
55ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3V
Address Bus
17b
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Number Of Ports
1
Supply Current
15mA
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Word Size
16b
Number Of Words
128K
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY62136VLL-55ZI
Manufacturer:
CYP
Quantity:
4 600
Part Number:
CY62136VLL-55ZI
Manufacturer:
CYPRESS
Quantity:
4 600
Part Number:
CY62136VLL-55ZI
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Cypress Semiconductor Corporation
Document #: 38-05087 Rev. *D
Features
Functional Description
The CY62136V is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
• High speed
• Temperature Ranges
• Wide voltage range
• Ultra-low active, standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in a Pb-free and non Pb-free 44-pin TSOP
Logic Block Diagram
— 55 ns
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
— 2.7V – 3.6V
Type II (forward pinout) and 48-ball FBGA packages
[1]
A
A
A
A
A
A
A
A
A
A
A
10
6
5
4
3
2
1
0
9
8
7
198 Champion Court
COLUMN DECODER
DATA IN DRIVERS
RAM Array
128K x 16
2-Mbit (128K x 16) Static RAM
This is ideal for providing More Battery Life™ (MoBL
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
deselected (CE HIGH). The input/output pins (I/O
I/O
(CE HIGH), outputs are disabled (OE HIGH), BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
written into the location specified on the address pins (A
through A
from I/O pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
LOW, then data from memory will appear on I/O
the Truth Table at the back of this data sheet for a complete
description of read and write modes.
15
) are placed in a high-impedance state when: deselected
16
San Jose
). If Byte High Enable (BHE) is LOW, then data
8
through I/O
,
CA 95134-1709
0
to I/O
I/O
I/O
7
0
8
. If Byte High Enable (BHE) is
15
– I/O
– I/O
0
CY62136V MoBL
Revised July 19, 2006
BHE
WE
CE
OE
) is written into the location
BLE
through A
7
15
0
16
through I/O
).
8
408-943-2600
to I/O
0
through
15
. See
®
7
) in
), is
®
0
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CY62136VLL-55ZI Summary of contents

Page 1

... A 0 Note: 1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05087 Rev. *D 2-Mbit (128K x 16) Static RAM This is ideal for providing More Battery Life™ (MoBL portable applications such as cellular telephones. The device ...

Page 2

... Product Portfolio V Range (V) CC [2] Product Min. Typ. CY62136VLL 2.7 3.0 [ Pin Configurations Notes: 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured pins are not connected on the die (DNU) pin have to be left floating or tied to V Document #: 38-05087 Rev ...

Page 3

... NC. This pin is not connected to the die is conducted BHE = LOW selects higher order byte WRITEs or READs on the SRAM BLE = LOW selects lower order byte WRITEs or READs on the SRAM behave as outputs. When deasserted HIGH, I/O pins are Tri-stated, and act as input data pins V ...

Page 4

Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature .................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +4.6V DC ...

Page 5

AC Test Loads and Waveforms OUTPUT OUTPUT INCLUDING JIG AND SCOPE (a) Parameters Data Retention Characteristics Parameter Description V V for Data Retention Data Retention ...

Page 6

Switching Characteristics Over the Operating Range Parameter Description Read Cycle t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t CE LOW to Data Valid ACE t OE LOW to Data ...

Page 7

Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) ADDRESS DATA OUT PREVIOUS DATA VALID [15, 16] Read Cycle No. 2 (OE Controlled) ADDRESS CE t ACE LZOE LZOE BHE/BLE t DBE t LZBE HIGH IMPEDANCE DATA ...

Page 8

Switching Waveforms (continued) [12, 17, 18] Write Cycle No. 1 (WE Controlled) ADDRESS BHE/BLE OE 19 DATA I/O NOTE t HZOE [12, 17, 18] Write Cycle No. 2 (CE Controlled) ADDRESS CE WE BHE/BLE OE DATA ...

Page 9

Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS CE BHE/BLE DATA I/O NOTE 19 t HZWE Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) ADDRESS CE BHE/BLE DATA I/O NOTE ...

Page 10

Typical DC and AC Characteristics Normalized Operating Current vs. Supply Voltage 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 1.7 2.2 SUPPLY VOLTAGE (V) Access Time vs. Supply Voltage 1.0 1.9 SUPPLY ...

Page 11

... Ordering Information Speed (ns) Ordering Code 55 CY62136VLL-55BAI CY62136VLL-55ZI CY62136VLL-55ZXI 70 CY62136VLL-70BAI CY62136VLL-70ZI CY62136VLL-70ZXI CY62136VLL-70ZSE CY62136VLL-70ZSXE Please contact your local Cypress sales representative for availability of these parts Package Diagrams TOP VIEW PIN 1 CORNER (LASER MARK 7.00±0.10 SEATING PLANE C Document #: 38-05087 Rev. *D Package Diagram Package Type 51-85096 48-ball Fine-Pitch Ball Grid Array ( ...

Page 12

... Document #: 38-05087 Rev. *D © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

Page 13

... Changed Package Name from ZS44 to Z44 for the 44 TSOP II Package Replaced ‘ZS’ with ‘Z’ in the Ordering Code for Industrial VKN Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court”. Added FBGA Package for Industrial Operating range. ...

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