CY62128LL-70ZRC Cypress Semiconductor Corp, CY62128LL-70ZRC Datasheet

CY62128LL-70ZRC

Manufacturer Part Number
CY62128LL-70ZRC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY62128LL-70ZRC

Density
1Mb
Access Time (max)
70ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
17b
Package Type
RTSOP
Operating Temp Range
0C to 70C
Number Of Ports
1
Supply Current
60mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Word Size
8b
Number Of Words
128K
Lead Free Status / Rohs Status
Not Compliant
Features
Functional Description
The CY62128 is a high-performance CMOS static RAM orga-
nized as 131,072 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE
chip enable (CE
three-state drivers. This device has an automatic power-down
Cypress Semiconductor Corporation
• 4.5V
• CMOS for optimum speed/power
• Low active power (70 ns, LL version)
• Low standby power (70 ns, LL version)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
Logic Block Diagram
WE
CE
CE
OE
— 330 mW (max.) (60 mA)
— 110 W (max.) (20 A)
1
2
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
V
CE
A
A
A
A
WE
A
A
NC
CC
A
A
A
A
A
A
5.5V operation
12
14
16
15
13
11
4
5
6
7
2
8
9
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
2
), an active LOW output enable (OE), and
INPUT BUFFER
512x 256x 8
DECODER
ARRAY
COLUMN
Reverse Pinout
(not to scale)
Top View
TSOP I
POWER
DOWN
1
, CE
2
1
, and OE options
), an active HIGH
3901 North First Street
62128-2
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
62128-1
A
A
A
A
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
CE
A
OE
3
2
1
0
10
0
1
2
3
4
5
6
7
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
CE
V
feature that reduces power consumption by more than 75%
when deselected.
Writing to the device is accomplished by taking chip enable
one (CE
two (CE
I/O
pins (A
Reading from the device is accomplished by taking chip en-
able one (CE
write enable (WE) and chip enable two (CE
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH or CE
during a write operation (CE
The CY62128 is available in a standard 450-mil-wide SOIC,
32-pin TSOP type I and STSOP packages.
WE
A
A
A
A
A
A
NC
A
A
CC
A
A
A
A
11
13
15
16
14
12
9
8
2
7
6
5
4
7
) is then written into the location specified on the address
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
2
1
through A
) input HIGH. Data on the eight I/O pins (I/O
) and write enable (WE) inputs LOW and chip enable
San Jose
2
1
LOW), the outputs are disabled (OE HIGH), or
) and output enable (OE) LOW while forcing
TSOP I/ STSOP
(not to scale)
16
Top View
128K x 8 Static RAM
).
Pin Configurations
GND
I/O
I/O
I/O
A
A
A
NC
A
A
A
A
A
A
A
A
1
16
14
12
7
6
5
4
3
2
1
0
0
1
2
LOW, CE
CA 95134
Top View
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
through I/O
SOIC
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
62128-2
HIGH, and WE LOW).
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CE
A
CE
I/O
I/O
I/O
I/O
I/O
V
A
WE
A
A
A
A
OE
10
CC
15
13
8
9
11
7
2
1
7
6
5
4
3
OE
A
CE
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
A
A
A
A
) are placed in a
CY62128
2
10
0
1
2
3
) HIGH. Under
1
7
6
5
4
3
2
1
0
June 18, 1998
408-943-2600
0
through
1

Related parts for CY62128LL-70ZRC

CY62128LL-70ZRC Summary of contents

Page 1

... Cypress Semiconductor Corporation feature that reduces power consumption by more than 75% when deselected. Writing to the device is accomplished by taking chip enable one (CE ) and write enable (WE) inputs LOW and chip enable 1 two (CE ) input HIGH. Data on the eight I/O pins (I then written into the location specified on the address ...

Page 2

Selection Guide Maximum Access Time (ns) Maximum Operating Current Maximum CMOS Standby Current Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. – +150 C Ambient Temperature with ...

Page 3

CY62128 ...

Page 4

Electrical Characteristics Over the Operating Range Parameter Description V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH [1] V Input LOW Voltage IL I Input Load Current IX I Output Leakage Cur- OZ rent ...

Page 5

AC Test Loads and Waveforms R1 1800 5V OUTPUT OUTPUT R2 100 pF 990 INCLUDING JIG AND SCOPE (a) Equivalent to: THÉVENIN EQUIVALENT 639 1.77V OUTPUT [6] Switching Characteristics Over the Operating Range Parameter READ CYCLE t Read Cycle Time ...

Page 6

Data Retention Characteristics Parameter Description V VCC for Data Retention DR I Data Retention Current Coml. CCDR [3] t Chip Deselect to Data Retention Time CDR [3] t Operation Recovery Time R Switching Waveforms [11,12] Read Cycle No.1 ADDRESS DATA ...

Page 7

Switching Waveforms (continued) Write Cycle No Controlled ADDRESS DATA I/O Write Cycle No. 2 (WE Controlled, OE HIGH During Write) ADDRESS ...

Page 8

Switching Waveforms (continued) Write Cycle No.3 (WE Controlled, OE LOW) ADDRESS NOTE 16 DATAI/O t HZWE Truth Table I/O – I ...

Page 9

CY62128 ...

Page 10

... CY62128L 70SI CY62128L 70ZI CY62128L-70ZAI CY62128L-70ZRI CY62128LL 70SC CY62128LL 70ZC CY62128LL-70ZAC CY62128LL-70ZRC CY62128LL 70SI CY62128LL-70ZI CY62128LL-70ZAI CY62128LL-70ZRI Document #: 38–00524–B © Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...

Page 11

... Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

Page 12

... Package Diagrams © Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

Page 13

... Reverse Thin Small Outline Package ZR32 © Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

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