ADMC401BST Analog Devices Inc, ADMC401BST Datasheet
ADMC401BST
Specifications of ADMC401BST
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ADMC401BST Summary of contents
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MIPS DSP CORE DATA ADDRESS GENERATORS PROGRAM SEQUENCER DAG 1 DAG 2 PROGRAM MEMORY ADDRESS EXTERNAL ADDRESS BUS DATA MEMORY ADDRESS PROGRAM MEMORY DATA EXTERNAL DATA BUS DATA MEMORY DATA ARITHMETIC UNITS ALU MAC SHIFTER High Performance Motor ...
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ADMC401–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter V Digital Supply Voltage DD AV Analog Supply Voltage DD T Ambient Operating Temperature AMB ELECTRICAL CHARACTERISTICS Parameter HI-Level Input Voltage LO-Level Input Voltage IL 1, ...
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ANALOG-TO-DIGITAL CONVERTER Parameter AC SPECIFICATIONS SNR Signal to Noise Ratio SNRD Signal to Noise and Distortion THD Total Harmonic Distortion CTLK Channel-Channel Crosstalk CMRR Common-Mode Rejection Ratio PSRR Power Supply Rejection Ratio ACCURACY INL Integral Nonlinearity DNL Differential Nonlinearity No ...
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... These are stresses only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ADMC401BST –40°C to +85°C ADMC401BSTZ –40C to +85 ...
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Parameter Clock Signals t is defined as 0.5t The ADMC401 uses an input clock CK CKI. with a frequency equal to half the instruction rate MHz clock (which is equivalent to 76.9 ns) yields a 38.5 ns processor ...
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ADMC401 Parameter Interrupts and Flags Timing Requirements: IRQx or FI Setup before CLKOUT Low t IFS IRQx or FI Hold after CLKOUT High t IFH Switching Characteristics: t Flag Output Hold after CLKOUT Low FOH t Flag Output Delay from ...
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Parameter Bus Request/Grant Timing Requirements: BR Hold after CLKOUT High Setup before CLKOUT Low t BS Switching Characteristics: CLKOUT High to DMS, PMS, BMS RD, WR Disable DMS, PMS, BMS, RD SDB Disable ...
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ADMC401 Parameter Memory Read Timing Requirements: RD Low to Data Valid t RDD A0–A13, PMS, DMS, BMS to Data Valid t AA Data Hold from RD High t RDH Switching Characteristics: RD Pulsewidth t RP CLKOUT High to RD Low ...
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Parameter Memory Write Switching Characteristics: Data Setup before WR High t DW Data Hold after WR High Pulsewidth Low to Data Enabled t WDE A0–A13, DMS, PMS Setup before WR Low t ASW Data ...
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ADMC401 Parameter Serial Ports Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP IN Switching Characteristics: t CLKOUT High to SCLK CC t SCLK High ...
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POWER DISSIPATION To determine total power dissipation in a specific application, the following equation should be applied for each output: C × V × load capacitance output switching frequency. Example application ...
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ADMC401 Pin Pin Pin No. Name No VDD GND ...
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CONVST GND 110 VDD 111 GND 112 AVDD 113 AVSS 114 VIN7 115 V 116 REF VIN6 117 REFCOM 118 VIN5 119 CAPT 120 VIN4 121 BSHAN 122 ASHAN 123 VIN0 124 CAPB 125 VIN1 126 CML 127 VIN2 ...
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ADMC401 (Continued from Page 1) GENERAL DESCRIPTION The ADMC401 is a single-chip DSP-based controller, suitable for high performance control of ac induction motors (ACIM), permanent magnet synchronous motors (PMSM), brushless dc motors (BDCM) and switched reluctance (SR) motors in indus- ...
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... Figure functional block diagram of the DSP core of the ADMC401. The DSP core is based on the fixed-point ADSP- 2171 core that is a member of the fixed-point ADSP-21xx family of general purpose DSPs from Analog Devices Inc. The ADSP-2171 flexible architecture and comprehensive in- struction set allow the processor to perform multiple operations in parallel ...
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ADMC401 Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches from data memory and pro- gram memory. Each DAG maintains and updates four address pointers (I registers). Whenever the pointer is used to access data (indirect addressing), ...
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PIN FUNCTION DESCRIPTION The ADMC401 is available in an 144-lead TQFP package. Table I contains the pin descriptions. Table I. Pin List Pin # Group of Input/ Name Pins Output Function A13– Address Lines D23–D0 24 I/O Data ...
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ADMC401 0x0000 2K INTERNAL RAM (BOOTED FROM BYTE-WIDE EPROM) 0x07FF 0x0800 2K INTERNAL ROM (ROMENABLE = 1) 2K EXTERNAL (ROMENABLE = 0) 0x0FFF 0x1000 12K EXTERNAL 0x3FFF MMAP = 0 BMODE = 0 When MMAP = 1 and BMODE = ...
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SYSTEM INTERFACE CLOCK SIGNALS The ADMC401 uses an input clock with a frequency equal to half the instruction rate MHz input clock yields a 38.5 ns processor cycle (which is equivalent to 26 MHz). Normally instructions are executed ...
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ADMC401 Two control lines indicate the direction of the transfer. Memory read, RD, is active low, signaling a read from external memory and memory write; WR, is active low, signaling a write to exter- nal memory. Typically, the PMS line ...
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The page length is read first and then bytes are loaded from the top of the page downwards. This causes shorter booting times for shorter pages. The length of the boot page is given as: page length = (number of ...
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ADMC401 Entering Power-Down The power-down sequence is initiated by applying a high-to-low transition on the PWD pin or by setting the power-down force control bit (PDFORCE) of the SPORT1 autobuffer/power- down control register. The DSP core then vectors to the ...
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BSHAN) to the inverting terminal of the two sample and hold amplifiers (SHA) so that external signals can be correctly biased about the nominal operating range of the ADC. ASHAN VIN0 SHA A VIN1 MUX VIN2 VIN3 12-BIT GAIN ...
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ADMC401 CONVERT START COMMAND The analog-to-digital conversion process of the ADMC401 may be started by either an internal or an external command. Bit 0 of the ADCCTRL register determines whether internal or external convert start mode is enabled. If Bit ...
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VIN0 (V) ASHAN (V) ≥2 × REF REF 2 × V – 1 LSB V REF REF 2 × V – 2 LSB V REF REF LSB V REF REF V V REF REF V ...
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ADMC401 ADC6 is valid and Bit 3 is set when the data in ADC3 and ADC7 is valid. At the start of the next conversion sequence, all bits of the ADCSTAT register are cleared. Additionally, at the end of the ...
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The SENSE pin controls whether the A/D system operates with an internal or an external reference. For operation with the internal reference, the SENSE pin should be tied to the REFCOM pin. In this mode, the internally derived 2 V ...
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ADMC401 lower harmonic distortion in three-phase PWM inverters. This technique also permits closed loop controllers to change the average voltage applied to the machine windings at a faster rate and so permits faster closed loop bandwidths to be achieved. The ...
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For example, for a 26 MHz CLKOUT and a desired PWM = 100 µs), the correct value switching frequency of 10 kHz ( load into the PWMTM register is: × PWMTM = × × 2 ...
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ADMC401 cycle of the signals on CH and CL. The duty cycle registers are programmed in integer counts of the fundamental time unit and define the desired on-time of the high side PWM signal CK produced by the ...
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Full ON: The PWM for any pair of PWM signals is said to operate in FULL ON when the desired HI side output of the three-phase Timing Unit is in the ON state (LO) between successive PWMSYNC pulses. This ...
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ADMC401 signals, setting Bit 7 enables crossover on the BH/BL pair of PWM signals and setting Bit 6 enables crossover on the CH/CL pair of PWM signals. If crossover mode is enabled for any pair of PWM signals, the high ...
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PWMCHA PWMCHA AH 2 PWMDT AL [4 (GDCLK+1)] PWMTM PWM Polarity Control, PWMPOL Pin The polarity of the PWM signals produced at the output pins may be selected in hardware by the PWMPOL pin. Connecting the PWMPOL ...
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ADMC401 Table V. Fundamental Characteristics of PWM Generation Unit of ADMC401 (CLKOUT = 26 MHz) Parameter Counter Resolution Edge Resolution T Programmable Dead Time D Dead Time Increments T Programmable Minimum Pulsewidth MIN Minimum Pulsewidth Increments f PWM Switching Frequency ...
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EIU count error interrupt is generated. An additional status bit is provided in the EIUSTAT register that indicates the initialization state of the EIU. Until the EIUMAXCNT register is written to, the EIU is not ...
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ADMC401 rate of 1.08 MHz. In general, the maximum encoder rate that can be consistently recognized is given by CLKOUT f ENCMAX × Operation of both the input synchronization logic and the noise filters is ...
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EIZ pin. When the ZERO bit of the EIUCTRL register is cleared, the zero marker is not used to reset the ...
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ADMC401 asynchronous timing of encoder and DSP-reading events result, more accurate computations of the position and velocity of the motor shaft may be performed. The EET consists of a 16-bit encoder event timer, an encoder pulse decimator and ...
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Table VI. Fundamental Characteristics of Encoder Interface Unit of ADMC401 (At 26 MHz) Parameter f Encoder Input (EIA, EIB) Rate ENC f Quadrature Rate QUAD Encoder Loop Timer Timeout Rate T Minimum Encoder Pulsewidth MINENC EIU/EET Registers The structure and ...
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ADMC401 edge on any of them will instantaneously shut down the PWM. However, based on the particular PIO interrupt that is flagged, the user can easily determine the source of the shutdown. This permits the action of the interrupt service ...
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ETU REGISTERS The configuration of the ETU registers is shown at the end of the data sheet. AUXILIARY PWM TIMERS The ADMC401 provides two variable-frequency, variable duty- cycle, 8-bit, auxiliary PWM outputs that are available at the AUX1 and AUX0 ...
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ADMC401 WATCHDOG TIMER OVERVIEW The watchdog timer is used as a protection mechanism against unintentional software events causing the DSP to become stuck in infinite loops. It can be used to cause a complete DSP and peripheral reset in the ...
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Interrupt Configuration The IFC and ICNTL registers of the DSP core control and configure the interrupt controller of the DSP core. The IFC register is a 16-bit register that may be used to force and/or clear any of the eight ...
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ADMC401 2 ROM or E PROM. Clearing the UARTEN bit selects SPORT mode, so that SPORT1 is configured in a manner identical to the standard serial ports of the ADSP-21xx family. Following reset, the UARTEN bit is cleared so that ...
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Address Name 0x2000–0x2007 0x2008 PWMTM 0x2009 PWMDT 0x200A PWMPD 0x200B PWMGATE 0x200C PWMCHA 0x200D PWMCHB 0x200E PWMCHC 0x200F PWMSEG 0x2010 AUXCH0 0x2011 AUXCH1 0x2012 AUXTM0 0x2013 AUXTM1 0x2014 0x2015 MODECTRL 0x2016 SYSSTAT 0x2017 0x2018 WDTIMER 0x2019–0x201B 0x201C PICVECTOR 0x201D PICMASK ...
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ADMC401 Address Name 0x2046 PIOINTEN 0x2047 PIOFLAG 0x2048–0x204F 0x2050 ETUA0 0x2051 ETUB0 0x2052 ETUAA0 0x2053 ETUA1 0x2054 ETUB1 0x2055 ETUAA1 0x2056 ETUTIME 0x2057–0x205B 0x205C ETUCONFIG 0x205D ETUDIVIDE 0x205E ETUSTAT 0x205F ETUCTRL 0x2060 PWMSYNCWT 0x2061 PWMSWT 0x2062–0x206F 0x2070 EETN 0x2071 EETDIV ...
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IN RANGE 1 = OUT OF RANGE SIMULTANEOUS SAMPLING 01 = ...
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ADMC401 LOW-SIDE CHOPPING 1 = ENABLE 0 = DISABLE HIGH-SIDE CHOPPING AH/AL CROSSOVER 1 = ENABLE BH/BL CROSSOVER ...
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RECEIVED FIRST ZERO MARKER 0 = NOT RECEIVED EIS STATE EIZ STATE EIB STATE EIA STATE ...
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ADMC401 ...
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FALLING EDGE (PIOMODE = 0) = ACTIVE LOW (PIOMODE = RISING EDGE (PIOMODE = 0) = ACTIVE HIGH (PIOMODE = EDGE SENSITIVE 1 = LEVEL SENSITIVE PWM ...
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ADMC401 ETU1 MODE 0 = SINGLE SHOT 1 = FREE-RUNNING ETU1 INTERRUPT 0 = NEXT EVENT EVENT B ETU1 EVENT FALLING EDGE ...
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DISABLE INTERRUPT (MASK ENABLE INTERRUPT PWM TRIP INTERRUPT Default bit values are shown value is shown, the bit field is undefined at reset. Reserved ...
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ADMC401 INDEPENDENT AUXILIARY 0 = OFFSET PWM MODE 1 = DOUBLE UPDATE 0 = SINGLE UPDATE ...
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ICNTL (R/ DSP REGISTER IRQ0 SENSITIVITY IRQ1 SENSITIVITY IRQ2 SENSITIVITY INTERRUPT NESTING 1 = ENABLE DISABLE INTERRUPT FORCE IRQ2 SPORT0 TRANSMIT SPORT0 RECEIVE SOFTWARE1 SOFTWARE 0 SPORT1 TRANSMIT OR IRQ1 SPORT1 RECEIVE ...
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ADMC401 ASTAT (R/ SPORT0 ENABLE 1 = ENABLE DISABLED SPORT1 ENABLE 1 = ENABLE DISABLED SPORT1 ...
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DWAIT4 SPORT0_RX_WORDS1 (R/ CHANNEL ENABLE 0 = CHANNEL IGNORED SPORT0_RX_WORDS0 (R/ ...
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ADMC401 CLKODIS CLKOUT DISABLE CONTROL BIT BIASRND MAC BIASED ROUNDING CONTROL BIT TIREG TRANSMIT AUTOBUFFER I REGISTER TMREG TRANSMIT AUTOBUFFER MREGISTER Default bit values are shown value is shown, the bit ...
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XTALDELAY 4096 CYCLE DELAY ENABLE 1 = DELAY DELAY PDFORCE POWERDOWN FORCE PUCR POWERUP CONTEXT RESET ENABLE 1 = SOFT RESET (CONTEXT CLEAR RESUME EXECUTION FLAG OUT (READ ONLY) ...
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ADMC401 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) 0.003 (0.08) 0.006 (0.15) 0.002 (0.05) Only dimensions in mm are accurate. The inch equivalents are approximations rounded to three decimal places. Only the mm values are recommended for use in PCB layout. ...