ADMC331BST Analog Devices Inc, ADMC331BST Datasheet

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ADSP-2100 BASE ARCHITECTURE DATA ADDRESS GENERATORS DAG 1 DAG 2 ARITHMETIC UNITS MAC ALU FUNCTIONAL BLOCK DIAGRAM PROGRAM MEMORY ROM 2K 24 PROGRAM DATA PROGRAM RAM RAM SEQUENCER PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM ...

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ADMC331–SPECIFICATIONS Parameter ANALOG-TO-DIGITAL CONVERTER Signal Input Resolution Converter Linearity Zero Offset Channel-to-Channel Comparator Match Comparator Delay Current Source Current Source Linearity ELECTRICAL CHARACTERISTICS V Logic Low IL V Logic High IH V Low Level Output Voltage OL V Low Level ...

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TIMING PARAMETERS Parameter Clock Signals t is defined as 0 The ADMC331 uses an input clock with a frequency equal CK CKI to half the instruction rate MHz input clock (which is equivalent to 76.9 ns) ...

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ADMC331 Parameter Serial Ports Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP IN Switching Characteristics: t CLKOUT High to SCLK CC t SCLK High ...

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... Operating Temperature Range (Ambient – 40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (5 sec +280°C Temperature Model Range ADMC331BST –40°C to +85°C ADMC331-ADVEVALKIT ADMC331-PB CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection ...

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ADMC331 Pin Pin Pin Pin Pin No. Type Name No. Type 1 O/P VREF 21 2 SUP GND GND BIDIR PIO9 25 5 BIDIR PIO8 6 BIDIR PIO7 26 7 BIDIR PIO6 27 ...

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GENERAL DESCRIPTION The ADMC331 is a low cost, single-chip DSP-based controller, suitable for ac induction motors, permanent magnet synchro- nous motors, brushless dc motors, and switched reluctance motors. The ADMC331 integrates a 26 MIPS, fixed-point DSP ...

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ADMC331 DATA DATA ADDRESS ADDRESS GENERATOR GENERATOR #1 #2 INPUT REGS INPUT REGS ALU MAC OUTPUT REGS OUTPUT REGS DSP CORE ARCHITECTURE OVERVIEW Figure overall block diagram of the DSP core of the ADMC331, which is based ...

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Program memory can store both instructions and data, permit- ting the ADMC331 to fetch two operands in a single cycle— one from program memory and one from data memory. The ADMC331 can fetch an operand from on-chip program memory and ...

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ADMC331 PIN FUNCTION DESCRIPTION The ADMC331 is available in an 80-lead TQFP package. Table I contains the pin descriptions. Table I. Pin List Pin # Group of Input/ Name Pins Output Function RESET 1 I/P Processor Reset Input. SPORT0 5 ...

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Table IV. ROM Utilities Utility Address Function PER_RST 0x07F1 Reset Peripherals. UMASK 0x0DED Limits Unsigned Value to Given Range. PUT_VECTOR 0x0DF4 Facilitates User Setup of Vector Table. SMASK 0x0E06 Limits Signed Value to Given Range. ADMC_COS 0x0E26 Cosine Function. ADMC_SIN ...

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ADMC331 Boot Loading On power-up or reset, the ADMC331 is configured so that execution begins at the internal PM ROM at address 0x0800. This starts execution of the internal monitor function that first performs some initialization functions and copies a ...

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PWM CONFIGURATION PWM DUTY CYCLE REGISTERS REGISTERS PWMTM ( PWMDT ( PWMCHA ( PWMCHB ( PWMPD ( PWMCHC (15 . ...

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ADMC331 These registers, in conjunction with the three 16-bit duty-cycle registers (PWMCHA, PWMCHB and PWMCHC), control the output of the three-phase timing unit. PWM Switching Frequency, PWMTM Register The PWM switching frequency is controlled by the 16-bit read/ write PWM ...

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Width of the PWMSYNC Pulse, PWMSYNCWT Register The PWM controller of the ADMC331 produces an output PWM synchronization pulse at a rate equal to the PWM switch- ing frequency in single update mode and at twice the PWM frequency in ...

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ADMC331 where the subscript 1 refers to the value of that register during the first half cycle and the subscript 2 refers to the value during the second half cycle. The corresponding duty cycles are: + PWMCHA T (PWMCHA – ...

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PWMCHA PWMCHB PWMCHB PWMCHC PWMTM 1 PWMSR The SR mode can only be enabled by connecting the PWMSR pin to GND. There is no software means by which this mode can ...

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ADMC331 included with two separate control bits in the PWMGATE register. Typical PWM output signals with high frequency chopping enabled on both high side and low side signals are shown in Figure 10. Chopping of the high side PWM outputs ...

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An internal current source is made available for connection to the external timing capacitor on the ICONST pin. An external current source could also be used, if required. The four input ...

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ADMC331 To ensure that the full input range of the ADC is utilized necessary to select the capacitor so that at the maximum capaci- tance value and the minimum current source output, the ramp voltage will charge to ...

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AUXCH0 AUX0 2 AUXCH1 AUX1 2 (AUXTM0 + 1) 2 AUXCH0 AUX0 2 (AUXTM0 + 1) AUX1 2 AUXCH1 2 (AUXTM1 + 1) Auxiliary PWM Interface, Registers and Pins The registers of the auxiliary PWM ...

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ADMC331 The entire interrupt control system of the ADMC331 is config- ured and controlled by the IFC, IMASK and ICNTL registers of the DSP core and the IRQFLAG register for the PWMSYNC and PWMTRIP interrupts and PIOFLAG0, PIOFLAG1 and PIOFLAG2 ...

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Controls the PWM single/double update mode. 7. Controls the ADC conversion time modes. 8. Controls the AUXPWM mode. 9. Contains a status register (SYSSTAT) that indicates the state of the PWMTRIP, PWMPOL and PWMSR pins, the watchdog timer and ...

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ADMC331 Address Offset (HEX) (Decimal) 0x2000 0 0x2001 1 0x2002 2 0x2003 3 0x2004 4 0x2005 5 0x2006 6 0x2007 7 0x2008 8 0x2009 9 0x200A 10 0x200B 11 0x200C 12 0x200D 13 0x200E 14 0x200F 15 0x2010 16 0x2011 ...

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Address Name 0x3FFF SYSCNTL 0x3FFE MEMWAIT 0x3FFD TPERIOD 0x3FFC TCOUNT 0x3FFB TSCALE 0x3FFA SPORT0_RX_WORDS1 0x3FF9 SPORT0_RX_WORDS0 0x3FF8 SPORT0_TX_WORDS1 0x3FF7 SPORT0_TX_WORDS0 0x3FF6 SPORT0_CTRL_REG 0x3FF5 SPORT0_SCLKDIV 0x3FF4 SPORT0_RFSDIV 0x3FF3 SPORT0_AUTOBUF_CTRL 0x3FF2 SPORT1_CTRL_REG 0x3FF1 SPORT1_SCLKDIV 0x3FF0 SPORT1_RFSDIV 0x3FEF SPORT1_AUTOBUF_CTRL Table XI. DSP Core ...

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ADMC331 System Controller Registers The system controller includes three registers, MODECTRL, SYSSTAT and IRQFLAG registers. The format of these regis- ters is shown at the end of the data sheet. The MODECTRL register controls different multiplexing, PWM interrupt and operating ...

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A CHANNEL CROSSOVER CROSSOVER B CHANNEL CROSSOVER 1 = CROSSOVER C CHANNEL CROSSOVER Default bit values are shown; if ...

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ADMC331 LOW SIDE GATE CHOPPING 0 = DISABLE 1 = ENABLE HIGH SIDE GATE CHOPPING PWMPD (R/ ...

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...

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ADMC331 PIOINTEN0 (R/W) 12 ...

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Default bit values are shown value ...

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ADMC331 ADC1 ( ADC2 ( ADC3 ...

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AUXILIARY 0 = OFFSET MODE PWM SELECT 1 = INDEPENDENT MODE 0 = 1/2 DSP CLOCKOUT ADC FREQUENCY COUNTER 1 = DSP CLOCKOUT SELECT FREQUENCY MODE PWMSR 0 = NORMAL PIN STATUS 0 ...

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ADMC331 0 = DISABLE 1 = ENABLE 15 0 INTERRUPT FORCE IRQ2 SPORT0 TRANSMIT SPORT0 RECEIVE SOFTWARE 1 SOFTWARE 0 SPORT1 TRANSMIT OR IRQ1 SPORT1 RECEIVE OR IRQ0 TIMER PERIPHERAL (OR IRQ2) RESERVED (SET ...

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DISABLED SPORT0 ENABLE 1 = ENABLED 0 = DISABLED SPORT1 ENABLE 1 = ENABLED SYSCNTL ...

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ADMC331 0.030 (0.75) 0.020 (0.50) 0.006 (0.15) 0.002 (0.05) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 80-Lead Plastic Thin Quad Flatpack (TQFP) (ST-80) 0.640 (16.25) 0.620 (15.75) 0.553 (14.05) 0.063 (1.60) MAX 0.549 (13.95) 0.486 (12.35) TYP 80 61 ...