AD824AR Analog Devices Inc, AD824AR Datasheet - Page 15
![no-image](/images/manufacturer_photos/0/0/57/analog_devices_inc_sml.jpg)
AD824AR
Manufacturer Part Number
AD824AR
Description
Manufacturer
Analog Devices Inc
Type
General Purpose Amplifierr
Datasheet
1.AD824AR.pdf
(16 pages)
Specifications of AD824AR
Rail/rail I/o Type
Rail to Rail Output
Number Of Elements
4
Unity Gain Bandwidth Product
2MHz
Slew Rate
2V/us
Common Mode Rejection Ratio
60dB
Input Offset Voltage
1mV
Input Bias Current
12pA
Single Supply Voltage (typ)
5/9/12/15/18/24/28V
Dual Supply Voltage (typ)
±3/±5/±9/±12V
Voltage Gain In Db
120dB
Power Supply Rejection Ratio
70dB
Power Supply Requirement
Single/Dual
Shut Down Feature
No
Single Supply Voltage (min)
3V
Single Supply Voltage (max)
30V
Dual Supply Voltage (min)
±1.5V
Dual Supply Voltage (max)
±15V
Technology
BiCOM
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
14
Package Type
SOIC N
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD824AR
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD824AR-14
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD824AR-14-REEL
Manufacturer:
AD
Quantity:
1 240
Company:
Part Number:
AD824AR-16
Manufacturer:
AD
Quantity:
301
Part Number:
AD824AR-16
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD824AR16
Manufacturer:
STM
Quantity:
2 806
Part Number:
AD824ARZ
Manufacturer:
AD
Quantity:
20 000
Part Number:
AD824ARZ-14
Manufacturer:
ADI/亚德诺
Quantity:
20 000
* AD824 SPICE Macro-model
*
* Copyright 1994 by Analog Devices, Inc.
*
* Refer to “README.DOC” file for License Statement.
Use of this model indicates your acceptance with
the terms and provisions in the License Statement. *
* Node assignments
*
*
*
*
*
*
.SUBCKT AD824
1 2 99 50 25
*
* INPUT STAGE & POLE AT 3.1 MHz
*
R3 5
1.193E3
R4 6
1.193E3
CIN 1
4E-12
C2 5
19.229E-12
I1 4 50
IOS 1
1E-12
EOS 7
POLY(1) (12,98) 100E-6 1
J1 4 2
J2 4 7
*
* GAIN STAGE & DOMINANT POLE
*
EREF
0 (30,0) 1
R5 9
2.205E6
C3 9
54E-12
G1 98
(6,5) 0.838E-3
V1 8
-1
V2 98
-1
D1 9
DX
D2 8
DX
*
* COMMON-MODE GAIN NETWORK WITH ZERO AT 1 kHz *
R21 11
1E6
R22 12
100
C14 11
159E-12
E13 11
POLY(2) (2,98) (1,98) 0 0.5 0.5
*
* POLE AT 10 MHz
*
R23 18
1E6
C15 18
15.9E-15
REV. C
JX
JX
ARG/ADI
9/94, Rev. A *
noninverting input
| inverting input
| | positive supply
| | | negative supply
| | | | output
| | | | |
99
99
2
6
108E-6
2
1
5
6
98
98
25
9
98
10
10
9
12
98
12
98
98
98
–15–
G15 98
(9,98) 1E-6
*
* OUTPUT STAGE
*
ES 26
(18,98) 1
RS 26
500
IB1 98
2.404E-3
IB2 23
2.404E-3
D10 21
DY
D11 98
DY
C16 20
2E-12
C17 24
2E-12
DQ1 97
DQ
Q2 20
22 NPN
Q3 24
22 PNP
DQ2 24
DQ
Q5 25
97 PNP 20
Q6 25
51 NPN 20
VP 96
0
VN 51
0
EP 96
(99,0) 1
EN 52
(50,0) 1
R25 30
5E6
R26 30
5E6
FSY1
0 VP 1
FSY2
50VN 1
DC1 25
DX
DC2 50
DX
*
* MODELS USED
*
.MODEL JX NJF(BETA=3.2526E-3 VTO=-2.000 IS=2E-12) .MODEL
NPN NPN(BF=120 VAF=150 VAR=15 RB=2E3
+ RE=4 RC=550 IS=1E-16)
.MODEL PNP PNP(BF=120 VAF=150 VAR=15 RB=2E3 + RE=4
RC=750 IS=1E-16)
.MODEL DX D(IS=1E-15)
.MODEL DY D()
.MODEL DQ D(IS=1E-16)
.ENDS AD824
18
98
22
21
98
98
23
25
25
20
21
23
51
20
24
97
52
0
0
99
50
99
0
99
25
AD824