5962-9201001MXC Cypress Semiconductor Corp, 5962-9201001MXC Datasheet - Page 50

• Manufacturer Part Number: 5962-9201001MXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of 5962-9201001MXC

• Lead Free Status / Rohs Status: Not Compliant

DSCC FORM 2234
APR 97
SYSCLK
D7 – D0
A7 – A1
AM5 - AM0
BGIN3 -
BGIN0
BGOUT3 -
BGOUT0
BBSY
BCLR
DS1 - DS0
DTACK
BERR
LWORD
IACK
IACK
SYSRESET
ACFAIL
SYSFAIL
BR3 - BR0
AS
WRITE
Symbol
IN
DEFENSE SUPPLY CENTER COLUMBUS
MICROCIRCUIT DRAWING
COLUMBUS, OHIO 43216-5000
The VMEbus system reset signal is both an input and an open collector output. A LOW level on this
signal resets the internal logic of the device and asserts the signals HALT and RESET . These signals
remain asserted for a minimum of 200 ms. If the device is configured as VMEbus system controller, a
LOW level on IRESET asserts SYSRESET for a minimum of 200 ms.
The VME AC fail signal is an input. This should be driven by the VMEbus power monitor (if installed).
The device can be enabled to provide a local interrupt on the assertion of this signal.
The VMEbus system fail signal is both an input and an open collector output. As an output the
other than the device). This signal is asserted by the device after a global reset. It may be masked by
clearing ICR6[6] or by setting ICR7[7]. The device can also be enabled to provide a local interrupt on
the assertion of this signal.
The VMEbus system clock is a three-state output. This signal is driven by the device when configured
as system controller ( SCON asserted). The frequency driven is 1/4 of the frequency delivered to the
device CLK64M signal. To deliver the required 16 MHz on this signal, the device must run at 64 MHz.
The device does not use this signal internally for any purpose.
The VMEbus bus request signals are both inputs and open collector outputs.
The VMEbus daisy-chained bus-grant-in signals are inputs.
The VMEbus daisy-chained bus-grant-out signals are outputs.
The VMEbus bus-busy signal is both an input and a rescinding output.
The VMEbus bus-clear signal is both an input and a three-state output.
The VMEbus Iow-order data lines are both inputs and three-state outputs.
The VMEbus low-order address lines are both inputs and three-state outputs.
The VMEbus address strobe signal is both an input and rescinding output.
The VMEbus data strobe signals are both inputs and rescinding outputs.
The VMEbus data-transfer-acknowledge signal is both an input and a rescinding output.
The VMEbus bus-error signal is both an input and a rescinding output.
The VMEbus data-direction signal is both an input and a three-state output.
The VMEbus long-word signal is both an input and a three-state output.
The VMEbus address-modifier signals are both inputs and three-state outputs.
The VMEbus interrupt acknowledge signal is both an input and a three-state output.
The VMEbus daisy-chained interrupt-acknowledge-in signal is an input.
SYSFAIL signal is asserted when HALT has been detected asserted for more than 6 s (by a source
STANDARD
TABLE III. Pin description.
Name and function
SIZE
A
REVISION LEVEL
B
SHEET
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