CY7C341-30JC Cypress Semiconductor Corp, CY7C341-30JC Datasheet - Page 7

• Manufacturer Part Number: CY7C341-30JC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C341-30JC

• Family Name: MAX®
• Memory Type: EPROM
• # Macrocells: 192
• Number Of Usable Gates: 3750
• Frequency (max): 50MHz
• Propagation Delay Time: 30ns
• Number Of Logic Blocks/elements: 12
• # I/os (max): 64
• Operating Supply Voltage (typ): 5V
• In System Programmable: No
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 84
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-03034 Rev. *B
External Synchronous Switching Characteristics Over the Operating Range
t
t
t
t
t
t
t
t
t
f
f
f
f
t
Notes:
19. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register output signal to the input of the LAB
20. This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge triggering, the t
21. This specification is a measure of the delay associated with the internal register feedback path for an asynchronous clock to LAB logic array input. This delay
22. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can
23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate.
24. This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. This specification is determined by
25. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode
26. This parameter indicates the minimum time that the previous register output data is maintained on the output after an asynchronous register clock input applied
ACO1
ACO2
AS1
AS2
AH
AWH
AWL
ACF
AP
MAXA1
MAXA2
MAXA3
MAXA4
AOH
Parameter
logic array and then to a combinatorial output. This delay assumes no expanders are used in the logic of combinatorial output or the asynchronous clock input.
The clock signal is applied to the dedicated clock input pin and all feedback is within a single LAB. This parameter is tested periodically by sampling production
material.
given input is used to clock multiple registers with both positive and negative polarity, t
plus the asynchronous register set-up time, t
within the same LAB, and assumes there is no expander logic in the clock path and the clock input signal is applied to a dedicated input pin. This parameter is tested periodically
by sampling production material.
operate. It is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs, and that no expander logic is employed in the
clock signal path or data path.
This parameter is determined by the lesser of (1/t
as long as this frequency is less than 1/t
the least of 1/(t
by a clock signal applied to an external dedicated input pin.
to an external dedicated input pin.
AWH
Dedicated Asynchronous Clock Input
to Output Delay
Asynchronous Clock Input to Local
Feedback to Combinatorial Output
Dedicated Input or Feedback Set-up
Time to Asynchronous Clock Input
I/O Input Set-Up Time to
Asynchronous Clock Input
Input Hold Time from
Asynchronous Clock Input
Asynchronous Clock Input
HIGH Time
Asynchronous Clock Input
LOW Time
Asynchronous Clock to
Local Feedback Input
External Asynchronous
Clock Period (1/f
External Feedback Maximum
Frequency in Asynchronous Mode
1/(t
Maximum Internal
Asynchronous Frequency
Data Path Maximum Frequency in
Asynchronous Mode
Maximum Asynchronous Register
Toggle Frequency 1/(t
Output Data Stable Time from
Asynchronous Clock Input
+ t
AWL
ACO1
), 1/(t
+ t
AS1
AS1
[6, 20]
[6]
+ t
)
AH
ACO1
[22]
[6]
) or 1/t
MAX4
Description
.
AS1
ACO1
[24]
)
[21]
AWH
, is the minimum internal period for an internal asynchronously clocked state machine configuration. This delay is for feedback
ACF
. It assumes data and clock input signals are applied to dedicated input pins and no expander logic is used.
USE ULTRA37000™ FOR
[23]
[6]
[6]
[26]
+ t
+ t
AS1
ALL NEW DESIGNS
AWL
)) or (1/(t
)
[25]
[19]
[6]
AWH
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
+t
AWL
)). If register output states must also control external points, this frequency can still be observed
AWH
should be used for both t
Min.
33.3
33.3
20
20
20
20
50
50
40
40
50
50
15
15
11
11
5
5
6
6
9
9
7C341-25
Max
25
25
40
40
15
15
[6]
(continued)
AWH
Min.
33.3
33.3
27
27
14
14
25
25
27
27
40
40
40
40
15
15
11
11
7C341-30
6
6
8
8
and t
AWL
AWH
Max
.
30
30
46
46
18
18
and t
AWL
parameters must be swapped. If a
Min.
33.3
33.3
28.5
28.5
33.3
33.3
30
30
10
10
16
16
14
14
30
30
23
23
15
15
7C341-35
8
8
CY7C341
Max
35
35
55
55
22
22
Page 7 of 15
Unit
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns