CY7C144-15AC Cypress Semiconductor Corp, CY7C144-15AC Datasheet - Page 11

CY7C144-15AC

Manufacturer Part Number
CY7C144-15AC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C144-15AC

Density
64Kb
Access Time (max)
15ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
13b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
220mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Word Size
8b
Number Of Words
8K
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C144-15AC
Manufacturer:
CY
Quantity:
5 510
Part Number:
CY7C144-15AC
Manufacturer:
VISHAY
Quantity:
5 510
Part Number:
CY7C144-15AC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Switching Waveforms
Document #: 38-06034 Rev. *E
Notes
20. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal can
21. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
22. R/W must be HIGH during all address transitions.
23. Data I/O pins enter high impedance when OE is held LOW during write.
DATA OUT
ADDRESS
SEM OR CE
SEM OR CE
DATA OUT
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
placed on the bus for the required t
be as short as the specified t
ADDRESS
DATA IN
DATA IN
R/W
OE
R/W
Figure 9. Write Cycle No. 2: R/W Three-State Data I/Os (Either Port)
Figure 8. Write Cycle No. 1: OE Three-State Data I/Os (Either Port)
PWE
t
SA
.
SD
(continued)
. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can
t
SA
t
HZOE
t
SCE
t
t
SCE
AW
t
HIGH IMPEDANCE
AW
t
HZWE
t
WC
t
WC
t
PWE
t
PWE
t
PWE
SD
DATA VALID
t
SD
HIGH IMPEDANCE
DATAVALID
or (t
HZWE
+ t
SD
) to allow the I/O drivers to turn off and data to be
t
HD
t
t
HD
LZWE
t
[20, 21, 22]
HA
t
[20, 22, 23]
LZOE
CY7C144, CY7C145
t
HA
Page 11 of 20
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