CY7C09579V-83BBI Cypress Semiconductor Corp, CY7C09579V-83BBI Datasheet - Page 25

• Manufacturer Part Number: CY7C09579V-83BBI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09579V-83BBI

• Density: 1.125Mb
• Access Time (max): 18ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 45MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 15b
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Number Of Ports: 2
• Supply Current: 385mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 172
• Word Size: 36b
• Number Of Words: 32K
• Lead Free Status / Rohs Status: Not Compliant

Document Number: 38-06054 Rev. *D
Right Port Configuration
Right Port Operation
Readout of Internal Address Counter
Left Port Operation
Notes
78. BM, SIZE, and BE must be reconfigured 1 cycle before operation is guaranteed. BM, SIZE, and BE should remain static for any particular port configuration.
79. In x36 mode, BE input is a “Don’t Care.”
80. DQ represents data output of the chip.
81. x18 and x9 configuration apply to right port only.
Configuration
Configuration
Right Port x36
Right Port x18
Right Port x9
Left Port x36
x18
x18
x9
x9
BM
0
1
1
Control Pin
Address on 1st Cycle
B0
B1
B2
B3
BE
0
1
0
1
WA, A
[80]
A
A
A
0R–14R
6R–14R
0L–14L
0R–14R
[78, 79]
SIZE
Data on 1st Cycle
0
0
1
DQ
DQ
DQ
DQ
18R–35R
27R–35R
0R–17R
0R–8R
I/O Pins used on 1st Cycle
[81]
I/O
I/O
I/O
I/O
Data on 2nd Cycle
Configuration
3R–17R
2R–17R
3L–17L
0R–8R
DQ
DQ
DQ
DQ
18R–35R
18R–26R
x36
x18
0R–17R
9R–17R
x9
I/O
I/O
I/O
I/O
Address on 2nd
18–26
27–35
BA, WA, A
9–17
0–8
Data on 3rd Cycle
Effect
Byte Control
Byte Control
Cycle
DQ
Byte Control
Byte Control
DQ
-
-
-
18R–26R
9R–17R
-
-
0R–5R
I/O Pins used
I/O
I/O
I/O Pins used on 2nd
I/O
0R–35R
0R–17R
0R–8R
Data on 4th Cycle
CY7C09569V
CY7C09579V
I/O
DQ
Cycle
DQ
1R–8R
-
-
-
27R–35R
0R–8R
-
-
Page 25 of 32
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