CY7C0832V-133AC Cypress Semiconductor Corp, CY7C0832V-133AC Datasheet
CY7C0832V-133AC
Specifications of CY7C0832V-133AC
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CY7C0832V-133AC Summary of contents
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... North First Street • San Jose CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V Address Counter and Mask Register 2-Mbit 4-Mbit 9-Mbit (256K x 18) (512K x 18) CY7C0832V CY7C0833V 167 167 133 4.0 4.0 4.7 225 225 270 120 TQFP 144 FBGA 144 FBGA , CA 95134 • ...
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... Mirror Reg CLK L CNTINT L Interrupt INT L Logic Note: 1. CY7C0837V has 15 address CY7C0830V has 16 address bits, CY7C0831V has 17 address bits, CY7C0832V has 18 address bits and CY7C0833V has 19 address bits Document #: 38-06059 Rev. *K PRELIMINARY I/O I/O Control Control True Dual-Ported RAM Array Address ...
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... Leave this ball unconnected for CY7C0837V and CY7C0830V 4. Leave this ball unconnected for CY7C0837V, CY7C0830V and CY7C0831V 5. Leave this ball unconnected for CY7C0837V, CY7C0830V, CY7C0831V and CY7C0832V 6. These balls are not applicable for CY7C0833V device. They need to be tied to VDDIO. 7. These balls are not applicable for CY7C0833V device. They need to be tied to VSS. ...
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... CNTRST 21 L CNT/MSK 10L 11L A 27 12L 13L Notes: 9. Leave this pin unconnected for CY7C0830V 10. Leave this pin unconnected for CY7C0830V and CY7C0831V Document #: 38-06059 Rev. *K PRELIMINARY 120-pin Thin Quad Flat Pack (TQFP) Top View CY7C0830V / CY7C0831V / CY7C0832V CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V ...
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... JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally TDO three-stated except when captured data is shifted out of the JTAG TAP. V Ground Inputs Power Inputs. DD Document #: 38-06059 Rev. *K CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V PRELIMINARY Description . MAX CY7C0837V is asserted LOW when L Page ...
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... At least one of BE0, BE1 must be LOW. 14. A18x for CY7C0832V, therefore the Interrupt Addresses are 3FFFF and 3FFFE. A18x and A17x are NC for CY7C0831V, therefore the Interrupt addresses are 1FFFF and 1FFFE; A18x, A17x and A16x are NC for CY7C0830V, therefore the Interrupt Addresses are FFFF and FFFE;A18x, A17x, A16x and A15x are NC for CY7C0837V, therefore the Interrupt Addresses are 7FFF and 7FFE ...
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... Constantly hold the address value for multiple clock cycles Mask Reset Reset mask register to all 1s Mask Load Load mask register with value presented on the address lines Mask Readback Read out mask register value on address lines Reserved Operation undefined CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V [16, 17] Description Page ...
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... The mask register is loaded with the address value presented at the address lines. Not all values permit correct increment Document #: 38-06059 Rev. *K CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V PRELIMINARY operations. Permitted values are of the form 2 From the most significant bit to the least significant bit, permitted values have zero or more “0s,” one or more “1s,” or one “ ...
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... Figure 1. Counter, Mask, and Mirror Logic Block Diagram Document #: 38-06059 Rev. *K PRELIMINARY Mask Register Counter/ Address Register Load/Increment Mirror Counter Increment Logic Wrap 17 Bit 0 +1 Wrap 1 Detect CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V Address RAM Decode Array To Readback and Address Decode 17 Wrap To Counter [1] Page ...
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... The user can use these materials to easily integrate the devices into the board’s boundary scan environment. Further information can be found in the Cypress application note Using JTAG Boundary Scan For System in a Package (SIP) Dual-Port SRAMs. CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V ...
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... TDI TDI Figure 3. Scan Chain for 9Mb Device Reserved for version number. Defines Cypress part number for CY7C0832V Defines Cypress part number for CY7C0831V Defines Cypress part number for CY7C0830V Defines Cypress part number for CY7C0837V. Allows unique identification of the DP family device vendor. ...
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... Description Test Conditions ° Input Capacitance MHz 3.3V DD Output Capacitance Input Capacitance Output Capacitance CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V + 0.5V DD Ambient Temperature V DD 0°C to +70°C 3.3V±165 mV –40°C to +85°C 3.3V±165 mV -133 -100 Unit 2.4 2.4 0.4 0.4 2 ...
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... CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V 3. 590 Ω 435 Ω 90% 10% < -133 -100 CY7C0833V CY7C0833V Max. Min. Max. Min. Max. 133 133 100 7 ...
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... RSF t Master Reset to Counter Interrupt RSCNTINT Flag Reset Time Document #: 38-06059 Rev. *K CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V PRELIMINARY (continued) -167 -133 CY7C0837V CY7C0837V CY7C0830V CY7C0830V CY7C0833V CY7C0831V CY7C0831V CY7C0832V CY7C0832V Min. Max. Min. Max. Min. 0.6 0.6 2.3 2.5 0.6 0.6 4.0 4 4.0 0 4.4 4 ...
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... TCK Clock LOW to TDO Invalid TDOX Test Clock TCK Test Mode Select TMS Test Data-In TDI Test Data-Out TDO Document #: 38-06059 Rev. *K PRELIMINARY Description TMSS t TMSH t TDIS t TDIH t TDOX t TDOV CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V CY7C0837V/CY7C0830V CY7C0831V/CY7C0832V Unit CY7C0833V Min. Max. 10 MHz 100 TCYC Page ...
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... Document #: 38-06059 Rev. *K PRELIMINARY t RSR ACTIVE t CYC2 t CL2 A A n+1 n+2 t CD2 CKLZ following the next rising edge of the clock. IH with CNT/MSK = V IL CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V n n+1 t OHZ t OLZ t OE constantly loads the address on the rising edge of the CLK. IH Page n+2 ...
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... One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK. Document #: 38-06059 Rev. *K PRELIMINARY CD2 CD2 n+1 n CD2 CKHZ Q n READ NO OPERATION CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V CD2 CKHZ CKHZ CKLZ CD2 CKHZ CD2 CKLZ CKLZ A A n+3 n+4 t CD2 t CKLZ WRITE READ Page n+3 (B1) ...
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... ADDRESS Document #: 38-06059 Rev. *K PRELIMINARY [32, 35, 37, 38 n+1 n+2 n n+2 n+3 t CD2 OHZ READ WRITE [37] t SAD t SCN t CD2 n COUNTER HOLD READ WITH COUNTER CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V A A n+4 n+5 t CD2 READ t HAD t HCN Q n+2 READ WITH COUNTER Page n+4 Q n+3 ...
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... ADDRESS n INTERNAL A n ADDRESS t t SAD HAD ADS CNTEN t t SCN HCN D DATA WRITE EXTERNAL ADDRESS Document #: 38-06059 Rev. *K PRELIMINARY [38 n+1 n+1 n+2 WRITE WITH WRITE COUNTER COUNTER HOLD CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V n+2 n+3 n n+3 n+4 WRITE WITH COUNTER Page ...
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... ADDRESS 0 Notes: 39 BE0 – BE1 = LOW MRST = CNT/MSK = HIGH 40. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset. Document #: 38-06059 Rev. *K PRELIMINARY 0 t CD2 t CKLZ WRITE READ READ ADDRESS 0 ADDRESS 1 CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V CD2 ...
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... the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines. Document #: 38-06059 Rev. *K PRELIMINARY [41, 42, 43, 44 CA2 CM2 n CD2 CKHZ CKLZ Q n INCREMENT in next clock cycle. CKLZ . CKHZ CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V A A n+4 n+2 n n+1 n+2 n+3 Page ...
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... CCS Document #: 38-06059 Rev. *K PRELIMINARY [45, 46, 47 CKLZ n t CCS CD2 CNTRST = MRST = CNT/MSK = HIGH. 1 CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V violated, indeterminate data will be Read out. CCS + t ) after the rising edge of R_Port's clock. CYC2 CD2 + t ) after the rising edge of R_Port's clock. CYC2 CD2 Page ...
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... CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value. 51. The mask register assumed to have the value of 3FFFFh. 52. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value. Document #: 38-06059 Rev. *K CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V PRELIMINARY 3FFFE 3FFFF Last_Loaded ...
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... When CE changes state, deselection and Read happen after one cycle of latency. 60 LOW R/W = HIGH Document #: 38-06059 Rev. *K PRELIMINARY n SINT 7FFFF m m+1 [1, 16, 58, 59, 60] Outputs CE R/W DQ – High High OUT H X High-Z CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V A A n+2 n+3 t RINT A A m+3 m+4 Operation 17 Deselected Deselected Write Read Outputs Disabled Page ...
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... Speed Package (MHz) Ordering Code Name 167 CY7C0832V-167BBC BB144 167 CY7C0832V-167AC 133 CY7C0832V-133BBC BB144 CY7C0832V-133BBI BB144 133 CY7C0832V-133AC CY7C0832V-133AI 128K × 18 (2-Mbit) 3.3V Synchronous CY7C0831V Dual-Port SRAM Speed Package (MHz) Ordering Code Name 167 CY7C0831V-167BBC BB144 167 CY7C0831V-167AC 133 CY7C0831V-167BBC BB144 ...
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... 13.00±0.10 SEATING PLANE C Document #: 38-06059 Rev. *K PRELIMINARY 144 FBGA ( 1.6 MM) BB144 BOTTOM VIEW A B 0.15(4X) CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V Ø0. Ø0. +0.10 Ø0.50 (144X) -0. 5.50 1.00 11.00 13.00±0.10 DIMENSIONS IN MILLIMETERS REFERENCE JEDEC: PUBLICATION 95 DESIGN GUIDE 4.14D PKG. WEIGHT: 0.53 gms ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V PRELIMINARY CY7C0837V ...
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... Updated selection guide table and moved to the front page. Updated block diagram to reflect x18 configuration. Added preliminary status back due to the addition of the new devices. RYQ Minor Change: Correct the revision indicated on the footer. CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V SB3 SB3 , t for the CY7C0853V to 4.7 ns CKLZ Page ...