5962-9061102XA Cypress Semiconductor Corp, 5962-9061102XA Datasheet

5962-9061102XA

Manufacturer Part Number

5962-9061102XA

Description

Manufacturer

Cypress Semiconductor Corp

Datasheet

1.5962-9061102XA.pdf (6 pages)

Specifications of 5962-9061102XA

Memory Type

EPROM

# Macrocells

# I/os (max)

Operating Supply Voltage (typ)

In System Programmable

Operating Supply Voltage (min)

4.5V

Operating Supply Voltage (max)

5.5V

Operating Temp Range

-55C to 125C

Operating Temperature Classification

Military

Mounting

Through Hole

Pin Count

Package Type

Windowed CDIP

Lead Free Status / Rohs Status

Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

5962-9061102XA

Manufacturer:

Quantity:

Company:

BOSTOCK HK LIMITED

Part Number:

5962-9061102XA

Manufacturer:

Quantity:

1 234

Company:

BOSTOCK HK LIMITED

Part Number:

5962-9061102XA

Quantity:

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EPLD

Features

General Description

The Cypress Multiple Array Matrix (MAX®) family of EPLDs

provides a user-configurable, high-density solution to gener-

al-purpose logic integration requirements. With the combina-

tion of innovative architecture and state-of-the-art process, the

MAX EPLDs offer LSI density without sacrificing speed.

The MAX architecture makes it ideal for replacing large

amounts of TTL SSI and MSI logic. For example, a 74161

counter utilizes only 3% of the 128 macrocells available in the

CY7C342B. Similarly, a 74151 8-to-1 multiplexer consumes

less than 1% of the over 1,000 product terms in the

Max Family Members

Cypress Semiconductor Corporation

Macrocells

MAX Flip-Flops

MAX Latches

MAX Inputs

MAX Outputs

Packages

Key: P—Plastic DIP; H—Windowed Ceramic Leaded Chip Carrier; J—Plastic J-Lead Chip Carrier; R—Windowed Pin Grid Array;

W—Windowed Ceramic DIP; N—Plastic Quad Flat Pack

Notes:

PAL is a registered trademark of Advanced Micro Devices.

MAX is a registered trademark of Altera Corporation.

• Erasable, user-configurable CMOS EPLDs capable of

• 0.8-micron double-metal CMOS EPROM technology

• Advanced 0.65-micron CMOS technology to increase

• Multiple Array MatriX architecture optimized for speed,

LASH

implementing high-density custom logic functions

(CY7C34X)

performance (CY7C34XB)

density, and straightforward design implementation

— Programmable Interconnect Array (PIA) simplifies

— Flexible macrocells increase utilization

— Programmable clock control

— Expander product terms implement complex logic

When all expander product terms are used to implement latches.

With one output.

routing

functions

Feature

370, Warp, Warp Professional, and Warp Enterprise are trademarks of Cypress Semiconductor Corporation.

[2]

[1]

CY7C344(B)

28H,J,W,P

•

Multiple Array Matrix High-Density EPLDs

CY7C343(B)

3901 North First Street

44H,J

128

CY7C342B. This allows the designer to replace 50 or more

TTL packages with just one MAX EPLD. The family comes in

a range of densities, shown below. By standardizing on a few

MAX building blocks, the designer can replace hundreds of

different 7400 series part numbers currently used in most dig-

ital systems.

The family is based on an architecture of flexible macrocells

grouped together into Logic Array Blocks (LABs). Within the

LAB is a group of additional product terms called expander

product terms. These expanders are used and shared by the

macrocells, allowing complex functions of up to 35 product

terms to be easily implemented in a single macrocell. A Pro-

grammable Interconnect Array (PIA) globally routes all signals

within devices containing more than one LAB. This architec-

ture is fabricated on the Cypress 0.8-micron, double-lay-

er-metal CMOS EPROM process, yielding devices with signif-

icantly higher integration, density and system clock speed than

the largest of previous generation EPLDs. The CY7C34XB de-

vices are 0.65-micron shrinks of the original 0.8-micron family.

The CY7C34XBs offer faster speed bins for each device in the

Cypress MAX family.

The density and performance of the CY7C340 family is ac-

cessed using Cypress’s Warp™, Warp Professional™, or

Warp

state-of-the-art synthesis, fitting, simulation and other devel-

opment tools at a very low cost. Warp Professional or Warp

Enterprise are sophisticated CAE tool that include behavior-

al simulation, graphical waveform editing and more. Consult

the datasheets for Warp, Warp Professional and Warp Enter-

prise™ for more information about these development tools.

CY7C342B

68H,J,R

128

256

Enterprise™

•

San Jose

CY7C340 EPLD Family

84H,J 100R,N

CY7C346(B)

design

•

128

256

CA 95134

software.

•

Warp

CY7C341B

84H,J,R

408-943-2600

July 19, 2000

192

384

provides

Related parts for 5962-9061102XA

5962-9061102XA Summary of contents

Page 1

... With one output. PAL is a registered trademark of Advanced Micro Devices. MAX is a registered trademark of Altera Corporation. F 370, Warp, Warp Professional, and Warp Enterprise are trademarks of Cypress Semiconductor Corporation. LASH Cypress Semiconductor Corporation Multiple Array Matrix High-Density EPLDs CY7C342B. This allows the designer to replace 50 or more TTL packages with just one MAX EPLD ...

Page 2

DEDICATED INPUTS LOGIC BLOCK ARRAY (LAB) EXPANDER PRODUCT TERMS MACROCELLS PROGRAMMABLE INTERCONNECT ARRAY (PIA) Figure 1. Key MAX Features 2 CY7C340 EPLD Family MULTIPLE ARRAYS (LABS) DUAL I/O FEEDBACK C340–1 ...

Page 3

Functional Description The Logic Array Block The logic array block, shown in Figure 2, is the heart of the MAX architecture. It consists of a macrocell array, expander product term array, and an I/O block. The number of mac- rocells, ...

Page 4

PROGRAMMABLE MACROCELL INTERCONNECT FEEDBACKS SIGNALS (32 FOR 7C344 EXPANDER DEDICATED PRODUCT INPUTS TERMS (64 FOR 7C344) MACROCELL P-TERMS EXPANDER P-TERMS Figure 5. Expander Product Terms I/O OUTPUT ENABLE PRESET ARRAY CLOCK CLEAR MACROCELL FEEDBACK NOTE: ONE SYSTEM ...

Page 5

I/O Block Separate from the macrocell array is the I/O control block of the LAB. Figure 6 shows the I/O block diagram. The three-state buffer is controlled by a macrocell product term and the drives the I/O pad. The input ...

Page 6

... Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

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