AM29F016B-90EC AMD (ADVANCED MICRO DEVICES), AM29F016B-90EC Datasheet - Page 2

• Manufacturer Part Number: AM29F016B-90EC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29F016B-90EC

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 40mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

GENERAL DESCRIPTION
The Am29F016B is a 16 Mbit, 5.0 volt-only Flash mem-
ory organized as 2,097,152 bytes. The 8 bits of data
appear on DQ0–DQ7. The Am29F016B is offered in
48-pin and 40-pin TSOP, and 44-pin SO packages. The
device is also available in Known Good Die (KGD)
form. For more information, refer to publication number
21551. This device is designed to be programmed
in-system with the standard system 5.0 volt V
ply. A 12.0 volt V
operations. The device can also be programmed in
standard EPROM programmers.
This device is manufactured using AMD’s 0.32 µm pro-
cess technology, and offers all the features and bene-
fits of the Am29F016, which was manufactured using
0.5 µm process technology.
The standard device offers access times of 70, 90, 120,
and 150 ns, allowing high-speed microprocessors to
operate without wait states. To eliminate bus conten-
tion, the device has separate chip enable (CE#), write
enable (WE#), and output enable (OE#) controls.
The device requires only a single 5.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
2
PP
is not required for program or erase
CC
sup-
Am29F016B
algorithm—an internal algorithm that automatically pre-
programs the array (if it is not already programmed) be-
fore executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
CC
detector that automatically inhibits write opera-