MT46V8M16TG-75Z Micron Technology Inc, MT46V8M16TG-75Z Datasheet - Page 47
![](/photos/31/34/313420/66pin_tsop_sml.jpg)
MT46V8M16TG-75Z
Manufacturer Part Number
MT46V8M16TG-75Z
Description
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V8M16TG-75Z.pdf
(81 pages)
Specifications of MT46V8M16TG-75Z
Organization
8Mx16
Density
128Mb
Address Bus
14b
Access Time (max)
750ps
Maximum Clock Rate
266MHz
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
140mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
CAS Latency (CL)
Figure 22:
PDF: 09005aef816fd013/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN
CAS Latency
Note:
The CL is the delay, in clock cycles, between the registration of a READ command and
the availability of the first bit of output data. The latency can be set to 2, 2.5, or 3 (-5B
only) clocks, as shown in Figure 22. Reserved states should not be used, as unknown
operation or incompatibility with future versions may result.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available nominally coincident with clock edge n + m. Table 32 on page 48 indi-
cates the operating frequencies at which each CL setting can be used.
COMMAND
COMMAND
COMMAND
BL = 4 in the cases shown; shown with nominal
DQS
DQS
DQS
CK#
CK#
CK#
DQ
DQ
DQ
CK
CK
CK
READ
READ
READ
T0
T0
T0
CL = 2
CL = 2.5
CL = 3
47
NOP
NOP
NOP
T1
T1
T1
TRANSITIONING DATA
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2
T2
NOP
NOP
NOP
T2
128Mb: x4, x8, x16 DDR SDRAM
t
AC,
T2n
T2n
t
DQSCK, and
T3
T3
NOP
NOP
NOP
T3
DON’T CARE
©2004 Micron Technology, Inc. All rights reserved.
T3n
T3n
T3n
t
DQSQ.
Operations