MT4LC8M8C2TG-5 Micron Technology Inc, MT4LC8M8C2TG-5 Datasheet - Page 3

• Manufacturer Part Number: MT4LC8M8C2TG-5
• Manufacturer: Micron Technology Inc
• Type: EDOr

Specifications of MT4LC8M8C2TG-5

• Organization: 8Mx8
• Density: 64Mb
• Address Bus: 15b
• Access Time (max): 50ns
• Maximum Clock Rate: Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 155mA
• Pin Count: 32
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

GENERAL DESCRIPTION (continued)
uniquely addressed via the address bits. First, the row
address is latched by the RAS# signal, then the column
address is latched by CAS#. Both devices provide EDO-
PAGE-MODE operation, allowing for fast successive
data operations (READ, WRITE, or READ-MODIFY-
WRITE) within a given row.
in order to retain stored data.
DRAM ACCESS
as mentioned in the General Description. The data for
each location is accessed via the eight I/O pins (DQ0-
DQ7). A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. An EARLY
WRITE occurs when WE# is taken LOW prior to CAS#
falling. A LATE WRITE or READ-MODIFY-WRITE occurs
when WE# falls after CAS# is taken LOW. During
EARLY WRITE cycles, the data outputs (Q) will remain
High-Z, regardless of the state of OE#. During LATE
WRITE or READ-MODIFY-WRITE cycles, OE# must be
taken HIGH to disable the data outputs prior to apply-
ing input data. If a LATE WRITE or READ-MODIFY-
WRITE is attempted while keeping OE# LOW, no write
will occur, and the data outputs will drive read data
from the accessed location.
8 Meg x 8 EDO DRAM
D20_2.p65 – Rev. 5/00
ADDR
RAS#
CAS#
DQ
OE#
The 8 Meg x 8 DRAM must be refreshed periodically
Each location in the DRAM is uniquely addressable,
V
V
V
V
V
V
IOH
IOL
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
ROW
OPEN
COLUMN (A)
VALID DATA (A)
The DQs go back to
Low-Z if
t OD
t OES
t OE
t
OES is met.
OE# CONTROL of DQs
VALID DATA (A)
COLUMN (B)
Figure 1
3
EDO PAGE MODE
output buffers off (High-Z) with the rising edge of
CAS#. If CAS# went HIGH and OE# was LOW (active),
the output buffers would be disabled. The 8 Meg x 8
DRAM offers an accelerated page mode cycle by elimi-
nating output disable from CAS# HIGH. This option is
called EDO, and it allows CAS# precharge time (
occur without the output data going invalid (see READ
and EDO-PAGE-MODE READ waveforms in the noted
appendix).
MODE READ, except data is held valid after CAS#
goes HIGH, as long as RAS# and OE# are held LOW and
WE# is held HIGH. OE# can be brought LOW or HIGH
while CAS# and RAS# are LOW, and the DQs will
transition between valid data and High-Z. Using OE#,
there are two methods to disable the outputs and keep
them disabled during the CAS# HIGH time. The first
method is to have OE# HIGH when CAS# transitions
HIGH and keep OE# HIGH for
will disable the DQs, and they will remain disabled
(regardless of the state of OE# after that point) until
CAS# falls again. The second method is to have OE#
LOW when CAS# transitions HIGH and then bring OE#
HIGH for a minimum of
HIGH period. This will disable the DQs, and they will
remain disabled (regardless of the state of OE# after that
point) until CAS# falls again (see Figure 1). During
VALID DATA (B)
DRAM READ cycles have traditionally turned the
EDO operates like any DRAM READ or FAST-PAGE-
t OD
The DQs remain High-Z
until the next CAS# cycle
if
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t OEHC
t
OEHC is met.
COLUMN (C)
t
OEP anytime during the CAS#
VALID DATA (C)
The DQs remain High-Z
until the next CAS# cycle
if
t OEP
t
OEP is met.
t
t OD
OEHC thereafter. This
EDO DRAM
8 MEG x 8
COLUMN (D)
©2000, Micron Technology, Inc.
OBSOLETE
DON’T CARE
UNDEFINED
VALID DATA (D)
t
CP) to