E28F016SA-100 Intel, E28F016SA-100 Datasheet - Page 8

• Manufacturer Part Number: E28F016SA-100
• Manufacturer: Intel

Specifications of E28F016SA-100

• Density: 16Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 11.4 to 12.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 60mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

28F016SA
2.1 Lead Descriptions
8
A
A
A
DQ
DQ
CE
RP#
OE#
WE#
0
1
16
Symbol
– A
0
0
8
– A
#,CE
– DQ
– DQ
15
20
7
15
1
#
INPUT/OUTPUT LOW-BYTE DATA BUS: Inputs data and commands during CUI write
INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x16 data program
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Type
BYTE-SELECT ADDRESS: Selects between high and low byte when the
device is in x8 mode. This address is latched in x8 data programs. Not
used in x16 mode (i.e., the A
high).
WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte block.
A
addresses are latched during data programs.
BLOCK-SELECT ADDRESSES: Select 1 of 32 erase blocks. These
addresses are latched during data programs, block erase and lock block
operations.
cycles. Outputs array, buffer, identifier or status data in the appropriate
read mode. Floated when the chip is deselected or the outputs are
disabled.
operations. Outputs array, buffer or identifier data in the appropriate read
mode; not used for Status Register reads. Floated when the chip is
deselected or the outputs are disabled.
CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers,
decoders and sense amplifiers. With either CE
is deselected and power consumption reduces to standby levels upon
completion of any current data program or block erase operations. Both
CE
All timing specifications are the same for both signals. Device selection
occurs with the latter falling edge of CE
CE
RESET/POWER-DOWN: RP# low places the device in a deep power-
down state. All circuits that burn static power, even those circuits enabled
in standby mode, are turned off. When returning from deep power-down,
a recovery time is required to allow these circuits to power-up.
When RP# goes low, any current or pending WSM operation(s) are
terminated, and the device is reset. All Status Registers return to ready
(with all status flags cleared).
OUTPUT ENABLE: Gates device data through the output buffers when
low. The outputs float to tri-state off when OE# is high.
CE x # overrides OE#, and OE# overrides WE#.
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue
Registers and Address Queue Latches. WE# is active low, and latches
both address and data (command or array) on its rising edge.
Page Buffer addresses are latched on the falling edge of WE#.
6–15
0
0
#, CE
# or CE
selects 1 of 1024 rows, and A
SEE NEW DESIGN RECOMMENDATIONS
1
# must be low to select the device.
1
# disables the device.
Name and Function
0
input buffer is turned off when BYTE# is
NOTE:
1–5
selects 16 of 512 columns. These
0
# or CE
0
# or CE
1
#. The first rising edge of
1
# high, the device