TE28F008B3BA110 Intel, TE28F008B3BA110 Datasheet - Page 57

• Manufacturer Part Number: TE28F008B3BA110
• Manufacturer: Intel

Specifications of TE28F008B3BA110

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 110ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 19b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 512K
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

11.3
11.3.1
11.4
Datasheet
Note: The Read Array command must be issued before data can be read from the memory array.
Read Status Register
The device Status Register indicates when a Program or Erase operation is complete, and the
success or failure of that operation. To read the Status Register, issue the Read Status Register
(70H) command to the CUI. This causes all subsequent Read operations to output data from the
Status Register until another command is written to the CUI. To return to reading from the array,
issue the Read Array (FFH) command.
The Status Register bits are output on DQ
a Read Status Register command.
The contents of the Status Register are latched on the falling edge of OE# or CE#, which prevents
possible Bus errors that might occur if Status Register contents change while being read. CE# or
OE# must be toggled with each subsequent status read, or the Status Register will not indicate
completion of a Program or Erase operation.
When the WSM is active, SR.7 will indicate the status of the WSM; the remaining bits in the Status
Register indicate whether or not the WSM was successful in performing the preferred operation
(see
Clearing the Status Register
The WSM sets status bits 1 through 7 to “1,” and clears bits 2, 6, and 7 to “0,” but cannot clear
status bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4, and 5 indicate various error conditions,
these bits can be cleared only through the Clear Status Register (50H) command. By allowing the
system software to control the resetting of these bits, several operations can be performed (such as
cumulatively programming several addresses or erasing multiple blocks in sequence) before
reading the Status Register to determine if an error occurred during that series. Clear the Status
Register before beginning another command or sequence.
Program Mode
Programming is executed using a two-write sequence. The Program Setup command (40H) is
written to the CUI followed by a second write that specifies the address and data to be
programmed. The WSM will execute a sequence of internally timed events to program preferred
bits of the addressed location, then verify the bits are sufficiently programmed. Programming the
memory results in specific bits within an address location being changed to a “0.” If users attempt
to program “1”s, the memory cell contents do not change and no error occurs.
The Status Register indicates programming status: while the program sequence executes, status bit
7 is “0.” The Status Register can be polled by toggling either CE# or OE#. While programming, the
only valid commands are Read Status Register, Program Suspend, and Program Resume.
When programming is complete, the program-status bits must be checked. If the programming
operation was unsuccessful, SR.4 is set to indicate a program failure. If SR.3 is set, then V
not within acceptable limits, and the WSM did not execute the program command. If SR.1 is set, a
program operation was attempted on a locked block and the operation was aborted.
The Status Register must be cleared before attempting the next operation. Any CUI instruction can
follow after programming is completed; however, to prevent inadvertent Status Register reads, be
sure to reset the CUI to read-array mode.
Table 29 on page
60).
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
0
–DQ
7
. The upper byte, DQ
8
–DQ
15
, outputs 00H during
PP
was
57